Configuration Cache Management for Coarse-Grained Reconfigurable Architecture with Multi-Array. - Peng Cao 002; Yong Cai; Bo Liu 019; Weiwei Shan (CyberC, 2012)

Memory Bandwidth Optimization Strategy of Coarse-Grained Reconfigurable Architecture. - Peng Cao 002; Huiyan Jiang; Bo Liu 019; Weiwei Shan (CyberC, 2012)

Hybrid-Priority Configuration Cache Supervision Method for Coarse Grained Reconfigurable Architecture. - Bo Liu 019; Peng Cao 002; Jinjiang Yang (CyberC, 2012)

Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. - Bo Liu 019; Peng Cao 002; Min Zhu 001; Jun Yang 006; Leibo Liu; Shaojun Wei; Longxing Shi (IEICE Trans. Inf. Syst., 2012)

A Configuration Compression Approach for Coarse-Grain Reconfigurable Architecture for Radar Signal Processing. - Bo Liu 019; Wan-Yu Zhu; Yang Liu; Peng Cao 002 (CyberC, 2014)

Hierarchical Pipeline Optimization of Coarse Grained Reconfigurable Processor for Multimedia Applications. - Chen Mei; Peng Cao 002; Yang Zhang 132; Bo Liu 019; Leibo Liu (IPDPS Workshops, 2014)

A novel configuration context cache structure of reconfigurable systems. - Yu Gong; Bo Liu 019; Chen Mei; Rui-he Wang (ASICON, 2015)

A novel routing structure of coarse-grained reconfigurable architecture for radar application. - Bo Liu 019; Dongming Zhang; Wei-qi Ge; Yu Gong (ASICON, 2015)

Performance-Conscious Reconfiguration Structure for Large-Scale Coarse-Grained Reconfigurable System. - Bo Liu 019; Yu Gong; Rui-he Wang; Yang Liu (CyberC, 2015)

A Novel Design of Pipeline MDC-FFT Processor Based on Various Memory Access Mechanism. - Jinjiang Yang; Dongming Zhang; Yu Gong; Bo Liu 019 (CyberC, 2016)

Implementation and Verification of a High-Throughput Reconfigurable MIMO Detector. - Zhen Wang 019; Hai Qin; Yu Gong; Bo Liu 019 (CyberC, 2017)

Processing LSTM in memory using hybrid network expansion model. - Yu Gong; Tingting Xu; Bo Liu 019; Wei Ge; Jinjiang Yang; Jun Yang 006; Longxing Shi (SiPS, 2017)

An energy-efficient accelerator for hybrid bit-width DNNs. - Bo Liu 019; Xing Ruan; Mengwen Xia; Yu Gong; Jinjiang Yang; Wei Ge; Jun Yang 006 (SSCI, 2017)

E-ERA: An energy-efficient reconfigurable architecture for RNNs using dynamically adaptive approximate computing. - Bo Liu 019; Wei Dong; Tingting Xu; Yu Gong; Wei Ge; Jinjiang Yang; Longxing Shi (IEICE Electron. Express, 2017)

Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach. - Chao Wang 068; Peng Cao 002; Bo Liu 019; Jun Yang 006 (IEICE Electron. Express, 2017)

Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications. - Peng Cao 002; Bo Liu 019; Jinjiang Yang; Jun Yang 006; Meng Zhang; Longxing Shi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Deep Learning Modeling Attack Method for MISR-APUF Protection Structures. - Wei Ge; Ji Quan Huang; Bo Liu 019; Min Zhu 001; Yuan Cao 003 (APCCAS, 2018)

Design and Optimization of Reconfigurable Data Path for Communication Baseband Signal Processing. - Shan-shan Zhu; Hai Qin; Bo Liu 019; Jun Yang 006 (CyberC, 2018)

An Energy-efficient Reconfigurable Hybrid DNN Architecture for Speech Recognition with Approximate Computing. - Bo Liu 019; Shisheng Guo; Hai Qin; Yu Gong; Jinjiang Yang; Wei Ge; Jun Yang 006 (DSP, 2018)

A Power Analysis Attack Countermeasure Based on Random Execution. - Shenghua Chen; Wei Ge; Jinjiang Yang; Bo Liu 019; Jun Yang 006 (TrustCom/BigDataSE, 2018)

EERA-ASR: An Energy-Efficient Reconfigurable Architecture for Automatic Speech Recognition With Hybrid DNN and Approximate Computing. - Bo Liu 019; Hai Qin; Yu Gong; Wei Ge; Mengwen Xia; Longxing Shi (IEEE Access, 2018)

EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier. - Zhen Wang 019; Mengwen Xia; Bo Liu 019; Xing Ruan; Yu Gong; Jinjiang Yang; Wei Ge; Jun Yang 006 (IEICE Electron. Express, 2018)

A Double Dwell High Sensitivity GPS Acquisition Scheme Using Binarized Convolution Neural Network. - Zhen Wang 019; Yuan Zhuang 001; Jun Yang 006; Hengfeng Zhang; Wei Dong; Min Wang; Luchi Hua; Bo Liu 019; Longxing Shi (Sensors, 2018)

A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement. - Yongliang Zhou; Menglin Han; Mingyue Liu; Hao Cai 001; Bo Liu 019; Jun Yang 006 (NANOARCH, 2019)

EERA-KWS: A 163 TOPS/W Always-on Keyword Spotting Accelerator in 28nm CMOS Using Binary Weight Network and Precision Self-Adaptive Approximate Computing. - Bo Liu 019; Zhen Wang 019; Hu Fan; Jing Yang; Bo Liu 026; Wentao Zhu; Lepeng Huang; Yu Gong; Wei Ge; Longxing Shi (IEEE Access, 2019)

An Ultra-Low Power Always-On Keyword Spotting Accelerator Using Quantized Convolutional Neural Network and Voltage-Domain Analog Switching Network-Based Approximate Computing. - Bo Liu 019; Zhen Wang 019; Wentao Zhu; Yuhao Sun; Zeyu Shen 003; Lepeng Huang; Yan Li 056; Yu Gong; Wei Ge (IEEE Access, 2019)

ARA: Cross-Layer approximate computing framework based reconfigurable architecture for CNNs. - Yu Gong; Bo Liu 019; Wei Ge; Longxing Shi (Microelectron. J., 2019)

An energy-efficient voice activity detector using deep neural networks and approximate computing. - Bo Liu 019; Zhen Wang 019; Shisheng Guo; Huazhen Yu; Yu Gong; Jun Yang 006; Longxing Shi (Microelectron. J., 2019)

An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN. - Bo Liu 019; Yuhao Sun; Hao Cai 001; Zeyu Shen 003; Yu Gong; Lepeng Huang; Zhen Wang 019 (ACM Great Lakes Symposium on VLSI, 2020)

A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing. - Bo Liu 019; Yan Li 056; Lepeng Huang; Hao Cai 001; Wentao Zhu; Shisheng Guo; Yu Gong; Zhen Wang 019 (ACM Great Lakes Symposium on VLSI, 2020)

A High-throughput Low-area Entropy Source Based on Asynchronous Feedback Unit. - Ping Wang; Jinjiang Yang; Min Zhu 001; Bo Liu 019 (ICCSP, 2020)

Binarized Weight Neural-Network Inspired Ultra-Low Power Speech Recognition Processor with Time-Domain Based Digital-Analog Mixed Approximate Computing. - Bo Liu 019; Hao Cai 001; Yu Gong; Wentao Zhu; Yan Li 056; Wei Ge; Zhen Wang 019 (ISCAS, 2020)

QCNN Inspired Reconfigurable Keyword Spotting Processor With Hybrid Data-Weight Reuse Methods. - Yu Gong; Yan Li 056; Xiaoling Ding; Haichuan Yang; Zilong Zhang; Xuan Zhang; Wei Ge; Zhen Wang 019; Bo Liu 019 (IEEE Access, 2020)

Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing. - Hao Cai 001; Honglan Jiang; Yongliang Zhou; Menglin Han; Bo Liu 019 (CCF Trans. High Perform. Comput., 2020)

FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance. - Wei Ge; Shenxin Hu; Ji Quan Huang; Bo Liu 019; Min Zhu 001 (IEICE Electron. Express, 2020)

A Power Analysis Attack Countermeasure Based on Random Data Path Execution For CGRA. - Wei Ge; Shenghua Chen; Benyu Liu; Min Zhu 001; Bo Liu 019 (IEICE Trans. Inf. Syst., 2020)

A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor. - Bo Liu 019; Hao Cai 001; Zhen Wang 019; Yuhao Sun; Zeyu Shen 003; Wentao Zhu; Yan Li 056; Yu Gong; Wei Ge; Jun Yang 006; Longxing Shi (IEEE Trans. Circuits Syst., 2020)

MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing. - Yongliang Zhou; Hao Cai 001; Bo Liu 019; Weisheng Zhao; Jun Yang 006 (IEEE Trans. Circuits Syst., 2020)

A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM. - Yongliang Zhou; Hao Cai 001; Lei Xie; Menglin Han; Mingyue Liu; Shi Xu; Bo Liu 019; Weisheng Zhao; Jun Yang 006 (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Implementation of a CRNN-based low-power keyword recognition system on FPGA. - Limo Guo; PengXu Lin; Lei Guo; Bo Liu 019 (ASICON, 2021)

An Always-on Ultra-Low Power Speaker Verification Accelerator based on Binary Weighted Neural Network with System Co-optimization. - Haige Wu; Xuan Zhang; Xiaoling Ding; Ziyu Wang; Anfeng Xue; Yu Gong; Bo Liu 019 (ASICON, 2021)

Mutual Error Compensation based Area and Power efficient Approximate Multiplier. - Renyuan Zhang; Xuetao Wang; Ziyu Wang; Anfeng Xue; Haichuan Yang; Yu Gong; Bo Liu 019 (ASICON, 2021)

Low-Power Keyword Recognition Feature Extraction Circuit based on SRMFCC and Shared Multiplier for High Noise Background. - Zilong Zhang; Haichuang Yang; Xuan Zhang; Xiaoling Ding; Xuetao Wang; Yu Gong; Bo Liu 019 (ASICON, 2021)

A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition. - Bo Liu 019; Zeyu Shen 003; Lepeng Huang; Yu Gong; Zilong Zhang; Hao Cai 001 (DATE, 2021)

In-MRAM Computing Elements with Single-Step Convolution and Fully Connected for BNN/TNN. - Zhong-Jian Bian; Yanan Guo 004; Bo Liu 019; Hao Cai 001 (ICTA, 2021)

Cryogenic In-MRAM Computing. - Yaoru Hou; We Ge; Yanan Guo 004; Lirida A. B. Naviner; You Wang 002; Bo Liu 019; Jun Yang 006; Hao Cai 001 (NANOARCH, 2021)

Reconfigurable Approximate Multiplication Architecture for CNN-Based Speech Recognition Using Wallace Tree Tensor Multiplier Unit. - Junyi Qian; Yuanyuan Jiang; Zilong Zhang; Renyuan Zhang; Ziyu Wang; Bo Liu 019 (NANOARCH, 2021)

A survey of in-spin transfer torque MRAM computing. - Hao Cai 001; Bo Liu 019; Juntong Chen; Lirida A. B. Naviner; Yongliang Zhou; Zhen Wang 019; Jun Yang 006 (Sci. China Inf. Sci., 2021)

Spintronic Solutions for Approximate Computing. - You Wang 002; Hao Cai 001; Kaili Zhang; Bo Wu; Bo Liu 019; Deming Zhang; Weisheng Zhao (Approximate Computing, 2022)

Approximate Computing for Energy-Constrained DNN-Based Speech Recognition. - Bo Liu 019; Hao Cai 001; Zhen Wang 019; Jun Yang 006 (Approximate Computing, 2022)

Triple-Skipping Near-MRAM Computing Framework for AIoT Era. - Juntong Chen; Hao Cai 001; Bo Liu 019; Jun Yang 006 (DATE, 2022)

A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing. - Bo Liu 019; Hao Cai 001; Xuan Zhang; Haige Wu; Anfeng Xue; Zilong Zhang; Zhen Wang 019; Jun Yang 006 (DATE, 2022)

A CGP-based Efficient Approximate Multiplier with Error Compensation. - Qiao Shen 001; Renyuan Zhang; Hao Zhang 111; Hao Cai 001; Bo Liu 019; Jian Xiao (ICTA, 2022)

A TWN Inspired Speaker Verification Processor with Hardware-friendly Weight Quantization. - Xuanhao Zhang; Haige Wu; Renyuan Zhang; Zihang Xu; Hao Zhang 111; Bo Liu 019; Hao Cai 001 (ICTA, 2022)

A Low Power DNN-based Speech Recognition Processor with Precision Recoverable Approximate Computing. - Bo Liu 019; Xuetao Wang; Renyuan Zhang; Anfeng Xue; Ziyu Wang; Haige Wu; Hao Cai 001 (ISCAS, 2022)

Background Noise Adaptive Energy-Efficient Keywords Recognition Processor With Reusable DNN and Reconfigurable Architecture. - Guoqiang He; Xiaoling Ding; Minghao Zhou; Bo Liu 019; Li Li 003 (IEEE Access, 2022)

Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN processing. - Bo Liu 019; Zilong Zhang; Hao Cai 001; Reyuan Zhang; Zhen Wang 019; Jun Yang 006 (Sci. China Inf. Sci., 2022)

Bit-error-rate aware sensing-error correction interaction in spintronic MRAM. - Hao Cai 001; Xinfang Tong; Pengcheng Wu; Xinning Liu; Bo Liu 019 (J. Syst. Archit., 2022)

An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing. - Bo Liu 019; Ziyu Wang; Xuetao Wang; Renyuan Zhang; Anfeng Xue; Qiao Shen 001; Na Xie; Yu Gong; Zhen Wang 019; Jun Yang 006; Hao Cai 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell. - Hao Cai 001; Yanan Guo 004; Bo Liu 019; Mingyang Zhou 002; Juntong Chen; Xinning Liu; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Quality Driven Systematic Approximation for Binary-Weight Neural Network Deployment. - Yu Gong; Hao Cai 001; Haige Wu; Wei Ge; Hao Yan 002; Zhen Wang 019; Longxing Shi; Bo Liu 019 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network. - Bo Liu 019; Hao Cai 001; Zilong Zhang; Xiaoling Ding; Ziyu Wang; Yu Gong; Weiqiang Liu 001; Jinjiang Yang; Zhen Wang 019; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Writing-only in-MRAM computing paradigm for ultra-low power applications. - Bo Liu 019; Mingyue Liu; Yongliang Zhou; Xiaofeng Hong; Hao Cai 001; Lirida Alves de Barros Naviner (Microprocess. Microsystems, 2022)

Work-in-Process: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs. - Xingyu Xu 008; Qingwen Wei; Yang Zhang 132; Hao Cai 001; Bo Liu 019 (CASES, 2023)

An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis. - Qingwen Wei; Yang Zhang 132; Xingyu Xu 008; Hao Cai 001; Bo Liu 019 (ICTA, 2023)

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. - Hao Cai 001; Zhongjian Bian; Yaoru Hou; Yongliang Zhou; Jia-Le Cui; Yanan Guo 004; Xiaoyun Tian; Bo Liu 019; Xin Si; Zhen Wang 019; Jun Yang 006; Weiwei Shan (ISSCC, 2023)

A Reconfigurable Approximate Computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment. - Bo Liu 019; Anfeng Xue; Ziyu Wang; Na Xie; Xuetao Wang; Zhen Wang 019; Hao Cai 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms. - Hao Cai 001; Yaoru Hou; Mengdi Zhang; Bo Liu 019; Lirida Alves de Barros Naviner (IEEE Des. Test, 2023)

Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition. - Bo Liu 019; Hao Cai 001; Zilong Zhang; Xiaoling Ding; Renyuan Zhang; Yu Gong; Zhen Wang 019; Wei Ge; Jun Yang 006 (IEEE Des. Test, 2023)

Computing in-memory with cascaded spintronic devices for AI edge. - Zhongjian Bian; Bo Liu 019; Hao Cai 001 (Comput. Electr. Eng., 2023)

W-AMA: Weight-aware Approximate Multiplication Architecture for neural processing. - Bo Liu 019; Renyuan Zhang; Qiao Shen 001; Zeju Li; Na Xie; Yuanhao Wang 009; Chonghang Xie; Hao Cai 001 (Comput. Electr. Eng., 2023)

Unveiling Security MRAM-OTP Macro using MTJ Hard Breakdown Mechanism. - Jiongzhe Su; Haoran Du; Quanhai Zhu; Mingtao Chen; Keyang Zhang; Bo Liu 019; Hao Cai 001 (AsianHOST, 2024)

A 28nm 128-kb Exponent- and Mantissa-Computation-InMemory Dual-macro for Floating-point and INT CNNs. - An Guo 001; Xueshan Dong; Fangyuan Dong; Dongqi Li; Yiran Zhang; Jingmin Zhang; Yuchen Tang; Yuhui Shi; Xiao Tan; Bo Liu 019; Weiwei Shan; Hao Cai 001; et al. (A-SSCC, 2024)

FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow. - Bo Liu 019; Qingwen Wei; Yang Zhang 132; Xingyu Xu 008; Zihan Zou; Xinxiang Huang; Xin Si; Hao Cai 001 (DAC, 2024)

Small-Footprint Automatic Speech Recognition System using Two-Stage Transfer Learning based Symmetrized Ternary Weight Network. - Xuanhao Zhang; Hui Kou; Chenjie Xia; Hao Cai 001; Bo Liu 019 (ICASSP, 2024)

22 nm Ultra-Low Power MCU with 43.5nW/KB Sleep Retention Power for Automotive Grade-1 Applications. - Yibo Liu; Wen Wang; Hongjin Zhu; Longning Qi; Bo Liu 019; Xinning Liu; Jun Yang 006; Hao Cai 001 (ICTA, 2024)

An Index-free Coding Compression Mechanism for Vision Transformers. - Han Yan; Zihan Zou; Shikuang Chen; Chen Zhang; Guang Yang 036; Hao Cai 001; Bo Liu 019 (ICTA, 2024)

Cache-Like Dual-Port SOT-MRAM with Read-while-Write Access Strategy. - Keyang Zhang; Bo Liu 019; Hao Cai 001 (ICTA, 2024)

Live Demonstration: A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing. - Chenjie Xia; Xuanhao Zhang; Zihan Zou; Hao Cai 001; Bo Liu 019 (ISCAS, 2024)

Complementary Series-connected STT-MTJ for Time-based Computing-in-Memory. - Rong Zhou; Bo Liu 019; Xin Si; Hao Cai 001 (ISCAS, 2024)

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. - An Guo 001; Xi Chen 107; Fangyuan Dong; Jinwu Chen; Zhihang Yuan; Xing Hu 010; Yuanpeng Zhang; Jingmin Zhang; Yuchen Tang; Zhican Zhang; Gang Chen 023; Dawei Yang; et al. (ISSCC, 2024)

Sparsity-Oriented MRAM-Centric Computing for Efficient Neural Network Inference. - Jia-Le Cui; Yanan Guo 004; Juntong Chen; Bo Liu 019; Hao Cai 001 (IEEE Trans. Emerg. Top. Comput., 2024)

VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits. - Yu Gong; Bo Liu 019; Hao Cai 001; Longxing Shi; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

On-Chip-Registration Supported ASR Processor Using Two-Step Transfer-Learning TWN. - Bo Liu 019; Xuanhao Zhang; Hui Kou; Chenjie Xia; Zhen Wang 019; Hao Cai 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications. - Zeju Li; Qinfan Wang; Zihan Zou; Qiao Shen 001; Na Xie; Hao Cai 001; Hao Zhang 111; Bo Liu 019 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Layer-Wise Mixed-Modes CNN Processing Architecture With Double-Stationary Dataflow and Dimension-Reshape Strategy. - Bo Liu 019; Xinxiang Huang; Yang Zhang 132; Guang Yang 036; Han Yan; Chen Zhang; Zejv Li; Yuanhao Wang 009; Hao Cai 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication. - Bo Liu 019; Na Xie; Qingwen Wei; Guang Yang 036; Chonghang Xie; Weiqiang Liu 001; Hao Cai 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device. - Xilong Kang; Qingwen Wei; Ningyuan Li 004; Xingyu Xu 008; Hao Cai 001; Bo Liu 019 (ASP-DAC, 2025)

TWDP: A Vision Transformer Accelerator with Token-Weight Dual-Pruning Strategy for Edge Device Deployment. - Guang Yang 036; Xinming Yan; Hui Kou; Zihan Zou; Qingwen Wei; Hao Cai 001; Bo Liu 019 (ASP-DAC, 2025)

A 40nm 4Mb High-Reliability STT-MRAM Achieving 18ns Write-Time and 94.9% Wafer-Level-Die-Yield Across -55°C-to-125°C. - Yaoru Hou; Haoran Du; Jiongzhe Su; Yibo Liu; Zhenghan Fang; Jia-Le Cui; Shuyu Wang; Chenxing Liu-Sun; Xuezhao Wu; Zhihua Xiao; Bo Liu 019; Xin Si; et al. (CICC, 2025)

A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs. - Bo Liu 019; Xingyu Xu 008; Yang Zhang 132; Xilong Kang; Qingwen Wei; Zihan Zou; Jun Yang 006; Hao Cai 001; Xin Si (CICC, 2025)

14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. - Xi Chen 107; Shaochen Li; Zhican Zhang; Wentao Zheng; Xiao Tan; Yuchen Tang; Yuhui Shi; Lizheng Ren; Yibo Mai; Feiran Liu; Jinwu Chen; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching. - An Guo 001; Jingmin Zhang; Xingyu Pu; Yi Yang 001; Defa Wu; Yuchen Tang; Yuhui Shi; Yinghai Gao; Zhichao Liu; Bo Wang 023; Tianzhu Xiong; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers. - Xing Wang; Tianhui Jiao; Yi Yang 001; Shaochen Li; Dongqi Li; An Guo 001; Yuhui Shi; Yuchen Tang; Jinwu Chen; Zhican Zhang; Zhichao Liu; Bo Liu 019; et al. (ISSCC, 2025)

Serial Magnetoresistance Accumulation Supported Spiking Neural Network in STT-MRAM. - Xiaoyun Tian; Zhongjian Bian; Bo Liu 019; Xin Si; Hao Cai 001 (NewCAS, 2025)

KV-Cache Oriented Query-Aware Sparse Attention Accelerator With Cross-Stage Precision-Configurable Digital CIM. - Yang Zhang 132; Xilong Kang; Weixuan Wang; Yizhi Ding; Lizheng Ren; Yiran Zhang; Ruiqi Tan; Zhen Wang 019; Hao Cai 001; Bo Liu 019 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)