D-A converter based variation analysis for analog layout design. - Bo Liu 031; Toru Fujimura; Bo Yang 004; Shigetoshi Nakatake (ASP-DAC, 2010)

Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis. - Bo Liu 031; Qing Dong 002; Bo Yang 004; Jing Li 072; Shigetoshi Nakatake (ISQED, 2011)

CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects. - Yu Zhang; Bo Liu 031; Bo Yang 004; Jing Li 072; Shigetoshi Nakatake (ISQED, 2012)

Layout-Aware Variability Characterization of CMOS Current Sources. - Bo Liu 031; Bo Yang 004; Shigetoshi Nakatake (IEICE Trans. Electron., 2012)

Twin-row-style for MOS analog layout. - Bo Liu 031; Shigetoshi Nakatake; Bo Yang 004; Gong Chen 002 (ICECS, 2016)

Routability of twisted common-centroid capacitor array under signal coupling constraints. - Gong Chen 002; Bo Liu 031; Shigetoshi Nakatake; Bo Yang 004 (MWSCAS, 2016)

A multi-functional memory unit with PLA-based reconfigurable decoder. - Nobuyuki Yahiro; Bo Liu 031; Atsushi Nanri; Shigetoshi Nakatake; Yasuhiro Takashima; Gong Chen 002 (ReConFig, 2016)

A Ku-Band Low-Phase-Noise Cross-Coupled VCO in GaAs HBT Technology. - Jincan Zhang; Yuming Zhang; Hongliang Lu; Yimen Zhang; Bo Liu 031; Leiming Zhang; Jinchan Wang; Liwen Zhang 003 (J. Circuits Syst. Comput., 2016)

Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit. - Xuncheng Zou; Bo Liu 031; Shigetoshi Nakatake (ACM Great Lakes Symposium on VLSI, 2017)

Explicit layout pattern density controlling based on transistor-array-style. - Chao Geng; Bo Liu 031; Shigetoshi Nakatake (MWSCAS, 2017)

Analog Characterization Module with Data Converter-Coupled Signal Reconfiguration. - Daishi Isogai; Bo Liu 031; Yoritaka Ishiguchi; Shigetoshi Nakatake (NGCAS, 2017)

Routable and Matched Layout Styles for Analog Module Generation. - Bo Liu 031; Gong Chen 002; Bo Yang 004; Shigetoshi Nakatake (ACM Trans. Design Autom. Electr. Syst., 2018)

Density Optimization for Analog Layout Based on Transistor-Array. - Chao Geng; Bo Liu 031; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Design of a Low-Phase-Noise Ka-Band GaAs HBT VCO. - Jincan Zhang; Min Liu; Liwen Zhang 003; Jinchan Wang; Bo Liu 031 (J. Circuits Syst. Comput., 2019)

An improved GaN P-HEMT small-signal equivalent circuit with its parameter extraction. - Jincan Zhang; Shaowei Wang; Min Liu; Bo Liu 031; Jinchan Wang (Microelectron. J., 2021)

Large-Signal Behavior Modeling of GaN P-HEMT Based on GA-ELM Neural Network. - Shaowei Wang; Jincan Zhang; Min Liu; Bo Liu 031; Jinchan Wang; Shi Yang (Circuits Syst. Signal Process., 2022)

A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout. - Bo Liu 031; Pengfei Wang; Kai Li 042; Binrui Xu; Jincan Zhang; Liwen Zhang 003 (Integr., 2022)

Hybrid small-signal modeling of GaN HEMTs based on improved genetic algorithm. - Jincan Zhang; Xuefeng Hou; Min Liu; Shi Yang; Bo Liu 031; Jinchan Wang; Juwei Zhang (Microelectron. J., 2022)

IACRA: Lifetime Optimization by Invulnerability-Aware Clustering Routing Algorithm Using Game-Theoretic Approach for Wsns. - Jun Wang 064; Yadan Zhang; Chunyan Hu; Pengjun Mao; Bo Liu 031 (Sensors, 2022)

Adaptive particle swarm optimization based hybrid small-signal modeling of GaN HEMT. - Haiyi Cai; Jincan Zhang; Min Liu; Shi Yang; Shaowei Wang; Bo Liu 031; Juwei Zhang (Microelectron. J., 2023)

A multi-objective parameter optimization approach to maximize lifetime of wireless sensor networks inspired by spider web. - Jun Wang 064; Yadan Zhang; Xichao Wang; Pengjun Mao; Bo Liu 031 (J. Supercomput., 2023)

High-Efficiency Multiobjective Synchronous Modeling and Solution of Analog ICs. - Bo Liu 031; Weizhe Zhang; Kai Li 042; Wenjuan Duan; Min Liu; Qingduan Meng (Circuits Syst. Signal Process., 2023)

Discrimination strategy using machine learning technique for oestrus detection in dairy cows by a dual-channel-based acoustic tag. - Jun Wang 064; Yifei Si; Jianping Wang; Xiaoxia Li; Kaixuan Zhao; Bo Liu 031; Yu Zhou (Comput. Electron. Agric., 2023)

BP Neural Network Modeling and Solving Acceleration of Analog ICs. - Bo Liu 031; Weizhe Zhang; Wenjuan Duan; Qingduan Meng (Circuits Syst. Signal Process., 2023)

FDIA localization and classification detection in smart grids using multi-modal data and deep learning technique. - Jun Wang 064; Haoran Chen; Yifei Si; Yongai Zhu; Tianci Zhu; Shanshan Yin; Bo Liu 031 (Comput. Electr. Eng., 2024)

Erratum: A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology. - Jinchan Wang; Gefan Wang; Kai Li 042; Bo Liu 031 (J. Circuits Syst. Comput., 2024)

Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL. - Bo Liu 031; He Yang; Xiangjun Wang; Ruizhi Xiang; Jun Wang 064; Liwen Zhang 003 (Microelectron. J., 2024)

Response surface methodology based synchronous multi-performance optimization of CMOS low-dropout regulator. - Bo Liu 031; Pengfei Wang; Xiang Liu; Liwen Zhang 003 (Microelectron. J., 2024)

A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology. - Jinchan Wang; Gefan Wang; Kai Li 042; Bo Liu 031 (J. Circuits Syst. Comput., 2024)

EDRP-GTDQN: An adaptive routing protocol for energy and delay optimization in wireless sensor networks using game theory and deep reinforcement learning. - Ning Liu; Jun Wang 064; Fazhan Tao; Zhumu Fu; Bo Liu 031 (Ad Hoc Networks, 2025)

Nested chopper instrument amplifier with noise modulation for physiological signal sensing. - Bo Liu 031; Dong Zhang; Tianyu Liu; Kai Li 042; Jinchan Wang; Jun Wang 064 (Integr., 2025)