A Low-power High-reliability STT-MRAM Write Scheme with Real-time Voltage Sensing Module. - Hao Li; Hongmei Yu; Dongsheng Liu; Peng Liu; Bo Liu 063 (ASICON, 2019)

A Configurable Architecture of ANN in Hardware with Resource-Efficient Reusable Neuron. - Jiahao Lu; Xianghua Luo; Dongsheng Liu; Peng Liu; Bo Liu 063 (ASICON, 2019)

Novel smart card SoC memory architecture based on embedded STT-MRAM. - Kaiwen Lu; Fengze Yan; Xingjie Liu; Dongsheng Liu; Peng Liu; Bo Liu 063 (ASICON, 2019)

Towards Efficient Hardware Implementation of NTT for Kyber on FPGAs. - Cong Zhang; Dongsheng Liu; Xingjie Liu; Xuecheng Zou; Guangda Niu; Bo Liu 063; Quming Jiang (ISCAS, 2021)

Efficient Hardware Architecture of Convolutional Neural Network for ECG Classification in Wearable Healthcare Device. - Jiahao Lu; Dongsheng Liu; Zilong Liu; Xuan Cheng; Lai Wei; Cong Zhang; Xuecheng Zou; Bo Liu 063 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)