Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints. - Chau-Chin Huang; Hsin-Ying Lee; Bo-Qiao Lin; Sheng-Wei Yang; Chin-Hao Chang; Szu-To Chen; Yao-Wen Chang (ICCAD, 2015)

Redistribution layer routing for integrated fan-out wafer-level chip-scale packages. - Bo-Qiao Lin; Ting-Chou Lin; Yao-Wen Chang (ICCAD, 2016)

Graph-Based Logic Bit Slicing for Datapath-Aware Placement. - Chau-Chin Huang; Bo-Qiao Lin; Hsin-Ying Lee; Yao-Wen Chang; Kuo-Sheng Wu; Jun-Zhi Yang (DAC, 2017)

NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. - Chau-Chin Huang; Hsin-Ying Lee; Bo-Qiao Lin; Sheng-Wei Yang; Chin-Hao Chang; Szu-To Chen; Yao-Wen Chang; Tung-Chieh Chen; Ismail Bustany (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)