Bo Wu

According to our database1, Bo Wu authored at least 9 papers between 2014 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2018
A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018

A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS.
IEEE J. Solid State Circuits, 2018

2016
A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM.
IEEE J. Solid State Circuits, 2016

A 24.7 mW 65 nm CMOS SAR-Assisted CT ΔΣ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR.
IEEE J. Solid State Circuits, 2016

15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 40 nm CMOS Derivative-Free IF Active-RC BPF With Programmable Bandwidth and Center Frequency Achieving Over 30 dBm IIP3.
IEEE J. Solid State Circuits, 2015

A 0.073-mm<sup>2</sup> 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

An 85-225MHz Chebyshev-II active-RC BPF with programmable BW and CF achieving over 30dBm IIP3 in 40nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014


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