Bo Yang

Affiliations:
  • NVIDIA
  • Polytechnic Institute of New York University


According to our database1, Bo Yang authored at least 11 papers between 2003 and 2007.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2007
Power Optimization for Universal Hash Function Data Path Using Divide-and-Concatenate Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006
Secure Scan: A Design-for-Test Architecture for Crypto Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks.
IEEE Trans. Computers, 2006

A High-Speed Hardware Architecture for Universal Message Authentication Code.
IEEE J. Sel. Areas Commun., 2006

2005
Divide-and-concatenate: an architecture-level optimization technique for universal hash functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A High Speed Architecture for Galois/Counter Mode of Operation (GCM).
IACR Cryptol. ePrint Arch., 2005

A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004
High speed architectures for Leviathan: a binary tree based stream cipher.
Microprocess. Microsystems, 2004

Scan Based Side Channel Attack on Data Encryption Standard.
IACR Cryptol. ePrint Arch., 2004

Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
Divide and Concatenate: A Scalable Hardware Architecture for Universal MAC.
IACR Cryptol. ePrint Arch., 2003


  Loading...