Fast Shape Optimization of Metallization Patterns for DMOS Based Driver. - Bo Yang 004; Shigetoshi Nakatake; Hiroshi Murata (ISQED, 2008)

A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion. - Bo Yang 004; Hiroshi Murata; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

STI stress aware placement optimization based on geometric programming. - Jing Li 072; Bo Yang 004; Xiaochuan Hu; Qing Dong 002; Shigetoshi Nakatake (ACM Great Lakes Symposium on VLSI, 2009)

Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming. - Qing Dong 002; Bo Yang 004; Jing Li 072; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver. - Bo Yang 004; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

D-A converter based variation analysis for analog layout design. - Bo Liu 031; Toru Fujimura; Bo Yang 004; Shigetoshi Nakatake (ASP-DAC, 2010)

Structured analog circuit design and MOS transistor decomposition for high accuracy applications. - Bo Yang 004; Qing Dong 002; Jing Li 072; Shigetoshi Nakatake (ICCAD, 2010)

Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path. - Jing Li 072; Bo Yang 004; Qing Dong 002; Shigetoshi Nakatake (ISCAS, 2010)

Layout-aware variation evaluation of analog circuits and its validity on op-amp designs. - Kota Shinohara; Mihoko Hidaka; Jing Li 072; Qing Dong 002; Bo Yang 004; Shigetoshi Nakatake (ACM Great Lakes Symposium on VLSI, 2011)

Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis. - Bo Liu 031; Qing Dong 002; Bo Yang 004; Jing Li 072; Shigetoshi Nakatake (ISQED, 2011)

A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model. - Gong Chen 002; Bo Yang 004; Shigetoshi Nakatake; Zhangcai Huang; Yasuaki Inoue (ISCAS, 2012)

Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. - Qing Dong 002; Bo Yang 004; Gong Chen 002; Jing Li 072; Shigetoshi Nakatake (ISQED, 2012)

CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects. - Yu Zhang; Bo Liu 031; Bo Yang 004; Jing Li 072; Shigetoshi Nakatake (ISQED, 2012)

Layout-Aware Variability Characterization of CMOS Current Sources. - Bo Liu 031; Bo Yang 004; Shigetoshi Nakatake (IEICE Trans. Electron., 2012)

A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. - Gong Chen 002; Bo Yang 004; Yu Zhang; Qing Dong 002; Shigetoshi Nakatake (ACM Great Lakes Symposium on VLSI, 2013)

A comparator energy model considering shallow trench isolation stress by geometric programming. - Gong Chen 002; Yu Zhang; Bo Yang 004; Qing Dong 002; Shigetoshi Nakatake (ISQED, 2013)

Structured Analog Circuit and Layout Design with Transistor Array. - Bo Yang 004; Qing Dong 002; Jing Li 072; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming. - Yu Zhang; Gong Chen 002; Bo Yang 004; Jing Li 072; Qing Dong 002; Mingyu Li; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Twin-row-style for MOS analog layout. - Bo Liu 031; Shigetoshi Nakatake; Bo Yang 004; Gong Chen 002 (ICECS, 2016)

Routability of twisted common-centroid capacitor array under signal coupling constraints. - Gong Chen 002; Bo Liu 031; Shigetoshi Nakatake; Bo Yang 004 (MWSCAS, 2016)

DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout. - Gong Chen 002; Toru Fujimura; Qing Dong 002; Shigetoshi Nakatake; Bo Yang 004 (ACM Trans. Design Autom. Electr. Syst., 2016)

Routable and Matched Layout Styles for Analog Module Generation. - Bo Liu 031; Gong Chen 002; Bo Yang 004; Shigetoshi Nakatake (ACM Trans. Design Autom. Electr. Syst., 2018)