Tree-model based mapping for energy-efficient and low-latency Network-on-Chip. - Bo Yang 009; Thomas Canhao Xu; Tero Säntti; Juha Plosila (DDECS, 2010)

Change Function of 2D/3D Network-on-Chip. - Alexander Wei Yin; Thomas Canhao Xu; Bo Yang 009; Pasi Liljeberg; Hannu Tenhunen (CIT, 2011)

Hierarchical Agent Monitoring Design Platform - Towards Self-aware and Adaptive Embedded Systems. - Liang Guang; Bo Yang 009; Juha Plosila; Jouni Isoaho; Hannu Tenhunen (PECCS, 2011)

t(k)-SA: accelerated simulated annealing algorithm for application mapping on networks-on-chip. - Bo Yang 009; Liang Guang; Tero Säntti; Juha Plosila (GECCO, 2012)

Parameter-Optimized Simulated Annealing for Application Mapping on Networks-on-Chip. - Bo Yang 009; Liang Guang; Tero Säntti; Juha Plosila (LION, 2012)

Hierarchical Supporting Structure for Dynamic Organization in Many-core Computing Systems. - Liang Guang; Syed M. A. H. Jafri; Bo Yang 009; Juha Plosila; Hannu Tenhunen (PECCS, 2013)

Mapping multiple applications with unbounded and bounded number of cores on many-core networks-on-chip. - Bo Yang 009; Liang Guang; Tero Säntti; Juha Plosila (Microprocess. Microsystems, 2013)