Divide and Concatenate: A Scalable Hardware Architecture for Universal MAC. - Bo Yang 010; Ramesh Karri; David A. McGrew (IACR Cryptol. ePrint Arch., 2003)

Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. - Bo Yang 010; Kaijie Wu 001; Ramesh Karri (ITC, 2004)

Scan Based Side Channel Attack on Data Encryption Standard. - Bo Yang 010; Kaijie Wu 001; Ramesh Karri (IACR Cryptol. ePrint Arch., 2004)

High speed architectures for Leviathan: a binary tree based stream cipher. - Darshan Sonecha; Bo Yang 010; Ramesh Karri; David A. McGrew (Microprocess. Microsystems, 2004)

A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only). - Bo Yang 010; Nikhil Joshi; Ramesh Karri (FPGA, 2005)

A High Speed Architecture for Galois/Counter Mode of Operation (GCM). - Bo Yang 010; Sambit Mishra; Ramesh Karri (IACR Cryptol. ePrint Arch., 2005)

Divide-and-concatenate: an architecture-level optimization technique for universal hash functions. - Bo Yang 010; Ramesh Karri; David A. McGrew (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A High-Speed Hardware Architecture for Universal Message Authentication Code. - Bo Yang 010; Ramesh Karri; David A. McGrew (IEEE J. Sel. Areas Commun., 2006)

Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks. - Nikhil Joshi; Jayachandran Sundararajan; Kaijie Wu 001; Bo Yang 010; Ramesh Karri (IEEE Trans. Computers, 2006)

Secure Scan: A Design-for-Test Architecture for Crypto Chips. - Bo Yang 010; Kaijie Wu 001; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Power Optimization for Universal Hash Function Data Path Using Divide-and-Concatenate Technique. - Bo Yang 010; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)