Revisiting floorplan representations. - Bo Yao 004; Hongyu Chen 001; Chung-Kuan Cheng; Ronald L. Graham (ISPD, 2001)

Physical Planning Of On-Chip Interconnect Architectures. - Hongyu Chen 001; Bo Yao 004; Feng Zhou; Chung-Kuan Cheng (ICCD, 2002)

Balancing the Interconnect Topology for Arrays of Processors between Cost and Power. - Esther Y. Cheng; Feng Zhou; Bo Yao 004; Chung-Kuan Cheng; Ronald L. Graham (ICCD, 2002)

The Y-architecture: yet another on-chip interconnect solution. - Hongyu Chen 001; Bo Yao 004; Feng Zhou; Chung-Kuan Cheng (ASP-DAC, 2003)

An algebraic multigrid solver for analytical placement with layout based clustering. - Hongyu Chen 001; Chung-Kuan Cheng; Nan-Chi Chou; Andrew B. Kahng; John F. MacDonald; Peter Suaris; Bo Yao 004; Zhengyong Zhu (DAC, 2003)

Power network analysis using an adaptive algebraic multigrid approach. - Zhengyong Zhu; Bo Yao 004; Chung-Kuan Cheng (DAC, 2003)

A hierarchical three-way interconnect architecture for hexagonal processors. - Feng Zhou; Esther Y. Cheng; Bo Yao 004; Chung-Kuan Cheng; Ronald L. Graham (SLIP, 2003)

Floorplan representations: Complexity and connections. - Bo Yao 004; Hongyu Chen 001; Chung-Kuan Cheng; Ronald L. Graham (ACM Trans. Design Autom. Electr. Syst., 2003)

A multiple level network approach for clock skew minimization with process variations. - Makoto Mori; Hongyu Chen 001; Bo Yao 004; Chung-Kuan Cheng (ASP-DAC, 2004)

Floorplan Representation in VLSI. - Zhou Feng; Bo Yao 004; Chung-Kuan Cheng (Handbook of Data Structures and Applications, 2004)

Integrated algorithmic logical and physical design of integer multiplier. - Shuo Zhou; Bo Yao 004; Jianhua Liu; Chung-Kuan Cheng (ASP-DAC, 2005)

Improving the efficiency of static timing analysis with false paths. - Shuo Zhou; Bo Yao 004; Hongyu Chen 001; Yi Zhu 002; Chung-Kuan Cheng; Michael D. Hutton; Truman Collins; Sridhar Srinivasan; Nan-Chi Chou; Peter Suaris (ICCAD, 2005)

Unified quadratic programming approach for mixed mode placement. - Bo Yao 004; Hongyu Chen 001; Chung-Kuan Cheng; Nan-Chi Chou; Lung-Tien Liu; Peter Suaris (ISPD, 2005)

The Y architecture for on-chip interconnect: analysis and methodology. - Hongyu Chen 001; Chung-Kuan Cheng; Andrew B. Kahng; Ion I. Mandoiu; Qinke Wang; Bo Yao 004 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. - Shuo Zhou; Bo Yao 004; Hongyu Chen 001; Yi Zhu 002; Chung-Kuan Cheng; Michael D. Hutton (ASP-DAC, 2006)

Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. - Ling Zhang; Hongyu Chen 001; Bo Yao 004; Kevin Hamilton; Chung-Kuan Cheng (ISQED, 2007)

Efficient Timing Analysis With Known False Paths Using Biclique Covering. - Shuo Zhou; Bo Yao 004; Hongyu Chen 001; Yi Zhu 002; Michael D. Hutton; Truman Collins; Sridhar Srinivasan; Nan-Chi Chou; Peter Suaris; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals. - Ling Zhang; Yulei Zhang 002; Hongyu Chen 001; Bo Yao 004; Kevin Hamilton; Chung-Kuan Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2011)