Width and Timing-Constrained Wire Sizing for Critical Area Minimization. - Jin-Tai Yan; Bo-Yi Chiang; Shi-Qin Huang (APCCAS, 2006)

Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis. - Jin-Tai Yan; Bo-Yi Chiang; Zhi-Wei Chen (ICECS, 2006)

Timing-constrained yield-driven wire sizing for critical area minimization. - Jin-Tai Yan; Bo-Yi Chiang; Chia-Fang Lee (ISCAS, 2006)

Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. - Jin-Tai Yan; Bo-Yi Chiang (VLSI Design, 2007)

Timing-constrained yield-driven redundant via insertion. - Jin-Tai Yan; Zhi-Wei Chen; Bo-Yi Chiang; Yu-Min Lee (APCCAS, 2008)