Resource allocation in D2D communication - A game theoretic approach. - Bo-Yuan Huang 001; Shih-Tang Su; Chih-Yu Wang 001; Che-Wei Yeh; Hung-Yu Wei 001 (ICC Workshops, 2014)

Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. - Bo-Yuan Huang 001; Yi-Hsiang Lai; Jie-Hong Roland Jiang (ICCAD, 2015)

Protocol Design and Game Theoretic Solutions for Device-to-Device Radio Resource Allocation. - Shih-Tang Su; Bo-Yuan Huang 001; Chih-Yu Wang 001; Che-Wei Yeh; Hung-Yu Wei 001 (IEEE Trans. Veh. Technol., 2017)

Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware. - Bo-Yuan Huang 001; Sayak Ray; Aarti Gupta; Jason M. Fung; Sharad Malik (DAC, 2018)

A formal instruction-level GPU model for scalable verification. - Yue Xing 001; Bo-Yuan Huang 001; Aarti Gupta; Sharad Malik (ICCAD, 2018)

Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification. - Pramod Subramanyan; Bo-Yuan Huang 001; Yakir Vizel; Aarti Gupta; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions. - Bo-Yuan Huang 001; Hongce Zhang; Aarti Gupta; Sharad Malik (TACAS (1), 2019)

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. - Bo-Yuan Huang 001; Hongce Zhang; Pramod Subramanyan; Yakir Vizel; Aarti Gupta; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 2019)

Intelligent REST API data fuzzing. - Patrice Godefroid; Bo-Yuan Huang 001; Marina Polishchuk (ESEC/SIGSOFT FSE, 2020)

Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables. - Yu Zeng; Bo-Yuan Huang 001; Hongce Zhang; Aarti Gupta; Sharad Malik (ICCAD, 2021)

Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface. - Bo-Yuan Huang 001; Steven Lyubomirsky; Yi Li; Mike He; Thierry Tambe; Gus Henry Smith; Akash Gaonkar; Vishal Canumalla; Gu-Yeon Wei; Aarti Gupta; Zachary Tatlock; Sharad Malik (CoRR, 2022)

INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms. - Bo-Yuan Huang 001; Hongce Zhang; Aarti Gupta; Sharad Malik (DAC, 2023)

Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface. - Bo-Yuan Huang 001; Steven Lyubomirsky; Yi Li; Mike He; Gus Henry Smith; Thierry Tambe; Akash Gaonkar; Vishal Canumalla; Andrew Cheung; Gu-Yeon Wei; Aarti Gupta; Zachary Tatlock; et al. (ACM Trans. Design Autom. Electr. Syst., 2024)