A Novel Pipelined Algorithm and Modular Architecture for Non-Square Matrix Transposition. - Bo Zhang 097; Zhenguo Ma; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT. - Hongji Fang; Bo Zhang 097; Feng Yu 003; Bei Zhao; Zhenguo Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Parallel Pipelined Architecture and Algorithm for Matrix Transposition Using Registers. - Bo Zhang 097; Zhenguo Ma; Wei Luo (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

General Adaptive Lossless Compression for Multi-Channel Sensor Signals. - Haori Zheng; Qianhao Chen; Feng Yu 003; Bo Zhang 097 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Optimised Serial Commutator FFT Architecture in Terms of Multiplexers. - Hongji Fang; Zhenguo Ma; Feng Yu 003; Bei Zhao; Bo Zhang 097 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Pulse Compression Shape-Based ADC/DAC Chain Synchronization Measurement Algorithm with Sub-Sampling Resolution. - Xiangyu Hao; Hongji Fang; Wei Luo; Bo Zhang 097 (Sensors, 2024)

Area-Efficient Pipeline Architecture for Serial Real-Valued Fast Fourier Transform. - Kun Li; Hongji Fang; Zhenguo Ma; Feng Yu 003; Bo Zhang 097; Qianjian Xing (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Fast Floating-Point Multiply-Accumulator Optimized for Sparse Linear Algebra on FPGAs. - Kun Li; Xiangyu Hao; Zhenguo Ma; Feng Yu 003; Bo Zhang 097; Qianjian Xing (IEEE Trans. Very Large Scale Integr. Syst., 2025)