Frequent value compression in packet-based NoC architectures. - Ping Zhou; Bo Zhao 007; Yu Du 002; Yi Xu 010; Youtao Zhang; Jun Yang 002; Li Zhao 002 (ASP-DAC, 2009)

A low-radix and low-diameter 3D interconnection network design. - Yi Xu 010; Yu Du 002; Bo Zhao 007; Xiuyi Zhou; Youtao Zhang; Jun Yang 002 (HPCA, 2009)

Energy reduction for STT-RAM using early write termination. - Ping Zhou; Bo Zhao 007; Jun Yang 002; Youtao Zhang (ICCAD, 2009)

A durable and energy efficient main memory using phase change memory technology. - Ping Zhou; Bo Zhao 007; Jun Yang 002; Youtao Zhang (ISCA, 2009)

Variation-tolerant non-uniform 3D cache management in die stacked multicore processor. - Bo Zhao 007; Yu Du 002; Youtao Zhang; Jun Yang 002 (MICRO, 2009)

Phase-Change Technology and the Future of Main Memory. - Benjamin C. Lee; Ping Zhou; Jun Yang 002; Youtao Zhang; Bo Zhao 007; Engin Ipek; Onur Mutlu; Doug Burger (IEEE Micro, 2010)

MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement. - Ping Zhou; Bo Zhao 007; Youtao Zhang; Jun Yang 002; Yiran Chen 001 (PACT, 2011)

Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors. - Lei Jiang 001; Bo Zhao 007; Youtao Zhang; Jun Yang 002 (DAC, 2012)

Architecting a common-source-line array for bipolar non-volatile memory devices. - Bo Zhao 007; Jun Yang 002; Youtao Zhang; Yiran Chen 001; Hai Li 001 (DATE, 2012)

Improving write operations in MLC phase change memory. - Lei Jiang 001; Bo Zhao 007; Youtao Zhang; Jun Yang 002; Bruce R. Childers (HPCA, 2012)

A speculative arbiter design to enable high-frequency many-VC router in NoCs. - Bo Zhao 007; Youtao Zhang; Jun Yang 002 (NOCS, 2013)

Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory. - Lei Jiang 001; Yu Du 002; Bo Zhao 007; Youtao Zhang; Bruce R. Childers; Jun Yang 002 (ACM Trans. Archit. Code Optim., 2013)

Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor. - Bo Zhao 007; Yu Du 002; Jun Yang 002; Youtao Zhang (IEEE Trans. Computers, 2013)

Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices. - Bo Zhao 007; Jun Yang 002; Youtao Zhang; Yiran Chen 001; Hai Li 001 (ACM Trans. Design Autom. Electr. Syst., 2013)

A low power and reliable charge pump design for Phase Change Memories. - Lei Jiang 001; Bo Zhao 007; Jun Yang 002; Youtao Zhang (ISCA, 2014)

Errata to "Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor". - Bo Zhao 007; Yu Du 002; Jun Yang 002; Youtao Zhang (IEEE Trans. Computers, 2014)

Throughput Enhancement for Phase Change Memories. - Ping Zhou; Bo Zhao 007; Jun Yang 002; Youtao Zhang (IEEE Trans. Computers, 2014)

Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology. - Lei Jiang 001; Bo Zhao 007; Jun Yang 002; Youtao Zhang (ACM Trans. Design Autom. Electr. Syst., 2015)

Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers. - Yi Xu 010; Bo Zhao 007; Youtao Zhang; Jun Yang 002 (ACM Trans. Parallel Comput., 2015)