A new philosophy for interconnection on multilayer boards. - B. Ramakrishna Rau (DAC, 1976)

The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units. - B. Ramakrishna Rau; George E. Rossman (ISCA, 1977)

Levels of representation of programs and the architecture of universal host machines. - B. Ramakrishna Rau (MICRO, 1978)

Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System. - B. Ramakrishna Rau (IEEE Trans. Computers, 1979)

Program Behavior and the Performance of Interleaved Memories. - B. Ramakrishna Rau (IEEE Trans. Computers, 1979)

Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. - B. Ramakrishna Rau; Christopher D. Glaeser (MICRO, 1981)

Systematically derived instruction sets for high-level language support. - Pradip Bose; B. Ramakrishna Rau; Michael S. Schlansker (ACM Southeast Regional Conference, 1982)

Architectural Support for the Efficient Generation of Code for Horizontal Architectures. - B. Ramakrishna Rau; Christopher D. Glaeser; E. M. Greenawalt (ASPLOS, 1982)

Efficient code generation for horizontal architectures: Compiler techniques and architectural support. - B. Ramakrishna Rau; Christopher D. Glaeser; Raymond L. Picard (ISCA, 1982)

Cydra 5 Directed Dataflow Architecture. - B. Ramakrishna Rau (COMPCON, 1988)

The Cydram 5 Stride-Insensitive Memory System. - B. Ramakrishna Rau; Michael S. Schlansker; David W. L. Yen (ICPP (1), 1989)

The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs. - B. Ramakrishna Rau; David W. L. Yen; Wei C. Yen; Ross A. Towle (Computer, 1989)

Appucations Development On the Very Long Instruction Word Cydra-5. - Peter Y.-T. Hsu; B. Ramakrishna Rau; K. J. M. Moriarty (Int. J. High Perform. Comput. Appl., 1989)

Pseudo-Randomly Interleaved Memory. - B. Ramakrishna Rau (ISCA, 1991)

Data Flow and Dependence Analysis for Instruction Level Parallelism. - B. Ramakrishna Rau (LCPC, 1991)

Sentinel Scheduling for VLIW and Superscalar Processors. - Scott A. Mahlke; William Y. Chen; Wen-mei W. Hwu; B. Ramakrishna Rau; Michael S. Schlansker (ASPLOS, 1992)

Code generation schema for modulo scheduled loops. - B. Ramakrishna Rau; Michael S. Schlansker; Parthasarathy P. Tirumalai (MICRO, 1992)

Register Allocation for Software Pipelined Loops. - B. Ramakrishna Rau; Meng Lee; Parthasarathy P. Tirumalai; Michael S. Schlansker (PLDI, 1992)

Predictability of load/store instruction latencies. - Santosh G. Abraham; Rabin A. Sugumar; Daniel Windheiser; B. Ramakrishna Rau; Rajiv Gupta (MICRO, 1993)

Dynamically scheduled VLIW processors. - B. Ramakrishna Rau (MICRO, 1993)

Reverse If-Conversion. - Nancy J. Warter; Scott A. Mahlke; Wen-mei W. Hwu; B. Ramakrishna Rau (PLDI, 1993)

Guest editors' introduction. - Joseph A. Fisher; B. Ramakrishna Rau (J. Supercomput., 1993)

Instruction-level parallel processing: History, overview, and perspective. - B. Ramakrishna Rau; Joseph A. Fisher (J. Supercomput., 1993)

Sentinel Scheduling for VLIW and Superscalar Processors. - Scott A. Mahlke; William Y. Chen; Roger A. Bringmann; Richard E. Hank; Wen-mei W. Hwu; B. Ramakrishna Rau; Michael S. Schlansker (ACM Trans. Comput. Syst., 1993)

Iterative modulo scheduling: an algorithm for software pipelining loops. - B. Ramakrishna Rau (MICRO, 1994)

Region-based compilation: an introduction and motivation. - Richard E. Hank; Wen-mei W. Hwu; B. Ramakrishna Rau (MICRO, 1995)

Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. - Chandra Chekuri; Richard Johnson; Rajeev Motwani 001; B. Natarajan; B. Ramakrishna Rau; Michael S. Schlansker (MICRO, 1996)

Iterative Modulo Scheduling. - B. Ramakrishna Rau (Int. J. Parallel Program., 1996)

Region-based compilation: Introduction, motivation, and initial experience. - Richard E. Hank; Wen-mei W. Hwu; B. Ramakrishna Rau (Int. J. Parallel Program., 1997)

Optimization of Machine Descriptions for Efficient Use. - John C. Gyllenhaal; Wen-mei W. Hwu; B. Ramakrishna Rau (Int. J. Parallel Program., 1998)

Automatic Architectural Synthesis of VLIW and EPIC Processors. - Shail Aditya; B. Ramakrishna Rau; Vinod Kathail (ISSS, 1999)

Machine-Description Driven Compilers for EPIC and VLIW Processors. - B. Ramakrishna Rau; Vinod Kathail; Shail Aditya (Des. Autom. Embed. Syst., 1999)

High-Level Synthesis of Nonprogrammable Hardware Accelerators. - Robert Schreiber; Shail Aditya; B. Ramakrishna Rau; Vinod Kathail; Scott A. Mahlke; Santosh G. Abraham; Greg Snider (ASAP, 2000)

Efficient design space exploration in PICO. - Santosh G. Abraham; B. Ramakrishna Rau (CASES, 2000)

The era of embedded computing. - B. Ramakrishna Rau (CASES, 2000)

Embedded Computing: New Directions in Architecture and Automation. - B. Ramakrishna Rau; Michael S. Schlansker (HiPC, 2000)

A Constructive Solution to the Juggling Problem in Processor Array Synthesis. - Alain Darte; Robert Schreiber; B. Ramakrishna Rau; Frédéric Vivien (IPDPS, 2000)

EPIC: Explicititly Parallel Instruction Computing. - Michael S. Schlansker; B. Ramakrishna Rau (Computer, 2000)

Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. - Shail Aditya; Scott A. Mahlke; B. Ramakrishna Rau (ACM Trans. Design Autom. Electr. Syst., 2000)

Embedded Computer Architecture and Automation. - B. Ramakrishna Rau; Michael S. Schlansker (Computer, 2001)

Compiling for EPIC architectures. - Vinod Kathail; Michael S. Schlansker; B. Ramakrishna Rau (Proc. IEEE, 2001)

PICO: Automatically Designing Custom Computers. - Vinod Kathail; Shail Aditya; Robert Schreiber; B. Ramakrishna Rau; Darren C. Cronquist; Mukund Sivaraman (Computer, 2002)

Constructing and exploiting linear schedules with prescribed parallelism. - Alain Darte; Robert Schreiber; B. Ramakrishna Rau; Frédéric Vivien (ACM Trans. Design Autom. Electr. Syst., 2002)

PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. - Robert Schreiber; Shail Aditya; Scott A. Mahlke; Vinod Kathail; B. Ramakrishna Rau; Darren C. Cronquist; Mukund Sivaraman (J. VLSI Signal Process., 2002)