Analysis of Continuous-Time Digital Signal Processors. - Bob Schell; Yannis P. Tsividis (ISCAS, 2007)

A Clockless ADC/DSP/DAC System with Activity-Dependent Power Dissipation and No Aliasing. - Bob Schell; Yannis P. Tsividis (ISSCC, 2008)

A Low Power Tunable Delay Element Suitable for Asynchronous Delays of Burst Information. - Bob Schell; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2008)

A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation. - Bob Schell; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2008)

Analysis and simulation of continuous-time digital signal processors. - Bob Schell; Yannis P. Tsividis (Signal Process., 2009)

A 3-12.5 Gb/s Reference-Less CDR for an Eye-Opening Monitor. - Bob Schell; Robert Bishop; Jack Kenney (ESSCIRC, 2018)

16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. - Hajime Shibata; Gerry Taylor; Bob Schell; Victor Kozlov; Sharvil Patil; Donald Paterson; Asha Ganesan; Yunzhi Dong; Wenhua Yang 002; Yue Yin; Zhao Li; Prawal Shrestha; et al. (ISSCC, 2020)