Modeling and synthesis of wide-band switched-resonators for VCOs. - Bodhisatwa Sadhu; Umaikhe E. Omole; Ramesh Harjani (CICC, 2008)

A CMOS 3.3-8.4 GHz wide tuning range, low phase noise LC VCO. - Bodhisatwa Sadhu; Jaehyup Kim; Ramesh Harjani (CICC, 2009)

Capacitor bank design for wide tuning range LC VCOs: 850MHz-7.1GHz (157%). - Bodhisatwa Sadhu; Ramesh Harjani (ISCAS, 2010)

An 8GHz multi-beam spatio-spectral beamforming receiver using an all-passive discrete time analog baseband in 65nm CMOS. - Satwik A. Patnaik; Sachin Kalia; Bodhisatwa Sadhu; Martin Sturm; Mohammad Elbadry; Ramesh Harjani (CICC, 2012)

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. - Jean-Olivier Plouchart; Mark A. Ferriss; Arun Natarajan 001; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aydin Babakhani; Soner Yaldiz; Lawrence T. Pileggi; Ramesh Harjani; et al. (CICC, 2012)

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. - Mark A. Ferriss; Jean-Olivier Plouchart; Arun Natarajan 001; Alexander V. Rylyakov; Benjamin D. Parker; Aydin Babakhani; Soner Yaldiz; Bodhisatwa Sadhu; Alberto Valdes-Garcia; José A. Tierno; Daniel J. Friedman (VLSIC, 2012)

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. - Shupeng Sun; Fa Wang; Soner Yaldiz; Xin Li 001; Lawrence T. Pileggi; Arun Natarajan 001; Mark A. Ferriss; Jean-Olivier Plouchart; Bodhisatwa Sadhu; Benjamin D. Parker; Alberto Valdes-Garcia; Mihai A. T. Sanduleanu; et al. (CICC, 2013)

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. - Mark A. Ferriss; Jean-Olivier Plouchart; Arun Natarajan 001; Alexander V. Rylyakov; Benjamin D. Parker; José A. Tierno; Aydin Babakhani; Soner Yaldiz; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Daniel J. Friedman (IEEE J. Solid State Circuits, 2013)

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. - Bodhisatwa Sadhu; Mark A. Ferriss; Arun Natarajan 001; Soner Yaldiz; Jean-Olivier Plouchart; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Aydin Babakhani; Scott K. Reynolds; Xin Li 001; Lawrence T. Pileggi; et al. (IEEE J. Solid State Circuits, 2013)

Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS. - Bodhisatwa Sadhu; Martin Sturm; Brian M. Sadler; Ramesh Harjani (IEEE J. Solid State Circuits, 2013)

Multi-Beam Spatio-Spectral Beamforming Receiver for Wideband Phased Arrays. - Sachin Kalia; Satwik A. Patnaik; Bodhisatwa Sadhu; Martin Sturm; Mohammad Elbadry; Ramesh Harjani (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. - Jean-Olivier Plouchart; Mark A. Ferriss; Arun Natarajan 001; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aydin Babakhani; Soner Yaldiz; Larry T. Pileggi; Ramesh Harjani; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". - Bodhisatwa Sadhu; Mark A. Ferriss; Arun S. Natarajan 001; Soner Yaldiz; Jean-Olivier Plouchart; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Aydin Babakhani; Scott K. Reynolds; Xin Li 001; Lawrence T. Pillage; et al. (IEEE J. Solid State Circuits, 2013)

Building an on-chip spectrum sensor for cognitive radios. - Bodhisatwa Sadhu; Martin Sturm; Brian M. Sadler; Ramesh Harjani (IEEE Commun. Mag., 2014)

Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits. - Jean-Olivier Plouchart; Fa Wang; Xin Li 001; Benjamin D. Parker; Mihai A. T. Sanduleanu; Andreea Balteanu; Bodhisatwa Sadhu; Alberto Valdes-Garcia; Daniel J. Friedman (IEEE Des. Test, 2014)

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. - Shupeng Sun; Fa Wang; Soner Yaldiz; Xin Li 001; Lawrence T. Pileggi; Arun Natarajan 001; Mark A. Ferriss; Jean-Olivier Plouchart; Bodhisatwa Sadhu; Benjamin D. Parker; Alberto Valdes-Garcia; Mihai A. T. Sanduleanu; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. - Mark A. Ferriss; Bodhisatwa Sadhu; Alexander V. Rylyakov; Herschel A. Ainspan; Daniel J. Friedman (ISSCC, 2015)

W-band scalable phased arrays for imaging and communications. - Xiaoxiong Gu; Alberto Valdes-Garcia; Arun Natarajan 001; Bodhisatwa Sadhu; Duixian Liu; Scott K. Reynolds (IEEE Commun. Mag., 2015)

A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance. - Bodhisatwa Sadhu; Mark A. Ferriss; Alberto Valdes-Garcia (IEEE J. Solid State Circuits, 2015)

10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs. - Mark A. Ferriss; Bodhisatwa Sadhu; Alexander V. Rylyakov; Herschel A. Ainspan; Daniel J. Friedman (ISSCC, 2016)

7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication. - Bodhisatwa Sadhu; Yahya M. Tousi; Joakim Hallin; Stefan Sahl; Scott K. Reynolds; Orjan Renstrom; Kristoffer Sjogren; Olov Haapalahti; Nadav Mazor; Bo Bokinge; Gustaf Weibull; Håkan Bengtsson; et al. (ISSCC, 2017)

A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications. - Bodhisatwa Sadhu; Yahya M. Tousi; Joakim Hallin; Stefan Sahl; Scott K. Reynolds; Orjan Renstrom; Kristoffer Sjogren; Olov Haapalahti; Nadav Mazor; Bo Bokinge; Gustaf Weibull; Håkan Bengtsson; et al. (IEEE J. Solid State Circuits, 2017)

Introduction to the Special Section on the 2016 IEEE BCTM and IEEE CSICS. - Bodhisatwa Sadhu; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2017)

Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions. - Alberto Valdes-Garcia; Bodhisatwa Sadhu; Xiaoxiong Gu; Jean-Olivier Plouchart; Mark Yeck; Daniel J. Friedman (BCICTS, 2018)

Circuit and antenna-in-package innovations for scaled mmWave 5G phased array modules. - Alberto Valdes-Garcia; Bodhisatwa Sadhu; Xiaoxiong Gu; Yahya M. Tousi; Duixian Liu; Scott K. Reynolds; Joakim Hallin; Stefan Sahl; Leonard Rexberg (CICC, 2018)

A 128-element Dual-Polarized Software-Defined Phased Array Radio for mm-wave 5G Experimentation. - Bodhisatwa Sadhu; Arun Paidimarri; Mark A. Ferriss; Mark Yeck; Xiaoxiong Gu; Alberto Valdes-Garcia (mmNets, 2018)

Antenna-in-package design and module integration for millimeter-wave communication and 5G. - Xiaoxiong Gu; Bodhisatwa Sadhu; Duixian Liu; Christian W. Baks; Alberto Valdes-Garcia (VLSI-DAT, 2018)

A Fully Decoupled LC Tank VCO Topology for Amplitude Boosted Low Phase Noise Operation. - Bodhisatwa Sadhu; Tejasvi Anand; Scott K. Reynolds (IEEE J. Solid State Circuits, 2018)

A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage. - Bodhisatwa Sadhu; Alberto Valdes-Garcia; Jean-Olivier Plouchart; Herschel A. Ainspan; Arpit K. Gupta; Mark A. Ferriss; Mark Yeck; Mihai Sanduleanu; Xiaoxiong Gu; Christian W. Baks; Duixian Liu; Daniel J. Friedman (IEEE J. Solid State Circuits, 2020)

Session 14 Overview: mm-Wave Transceivers for Communication and Radar Wireless Subcommittee. - Bodhisatwa Sadhu; Matteo Bassi; Vito Giannini (ISSCC, 2021)

A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams. - Bodhisatwa Sadhu; Arun Paidimarri; Wooram Lee; Mark Yeck; Caglar Ozdag; Yujiro Tojo; Jean-Olivier Plouchart; Xiaoxiong Gu; Yusuke Uemichi; Sudipto Chakraborty; Yo Yamaguchi; Ning Guan; et al. (ISSCC, 2022)

A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas. - Bodhisatwa Sadhu; Arun Paidimarri; Duixian Liu; Mark Yeck; Caglar Ozdag; Yujiro Tojo; Wooram Lee; Kevin Xiaoxiong Gu; Jean-Olivier Plouchart; Christian W. Baks; Yusuke Uemichi; Sudipto Chakraborty; et al. (IEEE J. Solid State Circuits, 2022)

A 24-30GHz Power Amplifier with >20-dBm Psat and <0.1-dB AM-AM Distortion for 5G Applications in 130-nm SiGe BiCMOS. - Chihiro Kamidaki; Yuma Okuyama; Tatsuo Kubo; Wooram Lee; Caglar Ozdag; Bodhisatwa Sadhu; Yo Yamaguchi; Ning Guan (IEICE Trans. Electron., 2023)

A 24 to 30-GHz Phased Array Transceiver Front End With 2.8 to 3.1-dB RX NF and 22 to 24% TX Peak Efficiency. - Wooram Lee; Caglar Ozdag; Jean-Olivier Plouchart; Alberto Valdes-Garcia; Bodhisatwa Sadhu (IEEE J. Solid State Circuits, 2024)

Cryogenic CMOS Circuits for Future Scaled Quantum Computing Systems: Challenges and Solutions. - Bodhisatwa Sadhu; Kevin Tien; Sudipto Chakraborty; David J. Frank; Pat Rosno; Daniel Moertl; Mark Yeck; John F. Bulzacchelli; Daniil Frolov; Devin Underwood; Ken Inoue; Christian W. Baks; et al. (CICC, 2025)