Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation. - Bogdan F. Romanescu; Michael E. Bauer; Daniel J. Sorin; Sule Ozev (PACT, 2007)

VariaSim: simulating circuits and systems in the presence of process variability. - Bogdan F. Romanescu; Michael E. Bauer; Sule Ozev; Daniel J. Sorin (SIGARCH Comput. Archit. News, 2007)

Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults. - Bogdan F. Romanescu; Daniel J. Sorin (PACT, 2008)

Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching. - Bogdan F. Romanescu; Michael E. Bauer; Sule Ozev; Daniel J. Sorin (Conf. Computing Frontiers, 2008)

Specifying and dynamically verifying address translation-aware memory consistency. - Bogdan F. Romanescu; Alvin R. Lebeck; Daniel J. Sorin (ASPLOS, 2010)

UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all. - Bogdan F. Romanescu; Alvin R. Lebeck; Daniel J. Sorin; Anne Bracy (HPCA, 2010)

Cost-effective Designs for Supporting Correct Execution and Scalable Performance in Many-core Processors. - Bogdan F. Romanescu (2010)

Address Translation Aware Memory Consistency. - Bogdan F. Romanescu; Alvin R. Lebeck; Daniel J. Sorin (IEEE Micro, 2011)