Bohan Yang

Orcid: 0000-0002-5204-1707

Affiliations:
  • Tsinghua University, Institute of Microelectronics, Beijing, China


According to our database1, Bohan Yang authored at least 14 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2024
A Low-Latency High-Order Arithmetic to Boolean Masking Conversion.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

UpWB: An Uncoupled Architecture Design for White-box Cryptography Using Vectorized Montgomery Multiplication.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

2023
A Closer Look at the Chaotic Ring Oscillators based TRNG Design.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

A Low-Randomness First-Order Masked Xoodyak.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

2022
A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance.
Sci. China Inf. Sci., 2022

A SHA-512 Hardware Implementation Based on Block RAM Storage Structure.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Efficient access scheme for multi-bank based NTT architecture through conflict graph.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Efficient Comparison and Addition for FHE With Weighted Computational Complexity Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020
Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

A High-performance Hardware Implementation of Saber Based on Karatsuba Algorithm.
IACR Cryptol. ePrint Arch., 2020


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