RECTANGLE: A Bit-slice Ultra-Lightweight Block Cipher Suitable for Multiple Platforms. - Wentao Zhang; Zhenzhen Bao; Dongdai Lin; Vincent Rijmen; Bohan Yang 001; Ingrid Verbauwhede (IACR Cryptol. ePrint Arch., 2014)

Highly efficient entropy extraction for true random number generators on FPGAs. - Vladimir Rozic; Bohan Yang 001; Wim Dehaene; Ingrid Verbauwhede (DAC, 2015)

Embedded HW/SW platform for on-the-fly testing of true random number generators. - Bohan Yang 001; Vladimir Rozic; Nele Mentens; Wim Dehaene; Ingrid Verbauwhede (DATE, 2015)

Challenges in designing trustworthy cryptographic co-processors. - Ricardo Chaves; Giorgio Di Natale; Lejla Batina; Shivam Bhasin; Baris Ege; Apostolos P. Fournaris; Nele Mentens; Stjepan Picek; Francesco Regazzoni 001; Vladimir Rozic; Nicolas Sklavos 001; Bohan Yang 001 (ISCAS, 2015)

On-the-fly tests for non-ideal true random number generators. - Bohan Yang 001; Vladimir Rozic; Nele Mentens; Ingrid Verbauwhede (ISCAS, 2015)

RECTANGLE: a bit-slice lightweight block cipher suitable for multiple platforms. - Wentao Zhang; Zhenzhen Bao; Dongdai Lin; Vincent Rijmen; Bohan Yang 001; Ingrid Verbauwhede (Sci. China Inf. Sci., 2015)

Extreme Pipelining Towards the Best Area-Performance Trade-Off in Hardware. - Stjepan Picek; Dominik Sisejkovic; Domagoj Jakobovic; Lejla Batina; Bohan Yang 001; Danilo Sijacic; Nele Mentens (AFRICACRYPT, 2016)

PRNGs for Masking Applications and Their Mapping to Evolvable Hardware. - Stjepan Picek; Bohan Yang 001; Vladimir Rozic; Jo Vliegen; Jori Winderickx; Thomas De Cnudde; Nele Mentens (CARDIS, 2016)

On the Feasibility of Cryptography for a Wireless Insulin Pump System. - Eduard Marin; Dave Singelée; Bohan Yang 001; Ingrid Verbauwhede; Bart Preneel (CODASPY, 2016)

TOTAL: TRNG on-the-fly testing for attack detection using Lightweight hardware. - Bohan Yang 001; Vladimir Rozic; Nele Mentens; Wim Dehaene; Ingrid Verbauwhede (DATE, 2016)

SOFIA: Software and control flow integrity architecture. - Ruan de Clercq; Ronald De Keulenaer; Bart Coppens 001; Bohan Yang 001; Pieter Maene; Koen De Bosschere; Bart Preneel; Bjorn De Sutter; Ingrid Verbauwhede (DATE, 2016)

IoT: Source of test challenges. - Erik Jan Marinissen; Yervant Zorian; Mario Konijnenburg; Chih-Tsun Huang; Ping-Hsuan Hsieh; Peter Cockburn; Jeroen Delvaux; Vladimir Rozic; Bohan Yang 001; Dave Singelée; Ingrid Verbauwhede; Cedric Mayor; et al. (ETS, 2016)

Iterating Von Neumann's post-processing under hardware constraints. - Vladimir Rozic; Bohan Yang 001; Wim Dehaene; Ingrid Verbauwhede (HOST, 2016)

Exploring active manipulation attacks on the TERO random number generator. - Yang Cao; Vladimir Rozic; Bohan Yang 001; Josep Balasch; Ingrid Verbauwhede (MWSCAS, 2016)

Evolving Cryptographic Pseudorandom Number Generators. - Stjepan Picek; Dominik Sisejkovic; Vladimir Rozic; Bohan Yang 001; Domagoj Jakobovic; Nele Mentens (PPSN, 2016)

On the Construction of Hardware-Friendly 4 times 4 and 5 times 5 S-Boxes. - Stjepan Picek; Bohan Yang 001; Vladimir Rozic; Nele Mentens (SAC, 2016)

Hold Your Breath, PRIMATEs Are Lightweight. - Danilo Sijacic; Andreas B. Kidmose; Bohan Yang 001; Subhadeep Banik; Begül Bilgin; Andrey Bogdanov; Ingrid Verbauwhede (SAC, 2016)

A Search Strategy to Optimize the Affine Variant Properties of S-Boxes. - Stjepan Picek; Bohan Yang 001; Nele Mentens (WAIFI, 2016)

Canary Numbers: Design for Light-weight Online Testability of True Random Number Generators. - Vladimir Rozic; Bohan Yang 001; Nele Mentens; Ingrid Verbauwhede (IACR Cryptol. ePrint Arch., 2016)

On-chip jitter measurement for true random number generators. - Bohan Yang 001; Vladimir Rozic; Milos Grujic; Nele Mentens; Ingrid Verbauwhede (AsianHOST, 2017)

A Privacy-Preserving Device Tracking System Using a Low-Power Wide-Area Network. - Tomer Ashur; Jeroen Delvaux; Sanghan Lee; Pieter Maene; Eduard Marin; Svetla Nikova; Oscar Reparaz; Vladimir Rozic; Dave Singelée; Bohan Yang 001; Bart Preneel (CANS, 2017)

Design of S-boxes Defined with Cellular Automata Rules. - Stjepan Picek; Luca Mariot; Bohan Yang 001; Domagoj Jakobovic; Nele Mentens (Conf. Computing Frontiers, 2017)

The Monte Carlo PUF. - Vladimir Rozic; Bohan Yang 001; Jo Vliegen; Nele Mentens; Ingrid Verbauwhede (FPL, 2017)

Lightweight Prediction-Based Tests for On-Line Min-Entropy Estimation. - Milos Grujic; Vladimir Rozic; Bohan Yang 001; Ingrid Verbauwhede (IEEE Embed. Syst. Lett., 2017)

Securing Wireless Neurostimulators. - Eduard Marin; Dave Singelée; Bohan Yang 001; Vladimir Volskiy; Guy A. E. Vandenbosch; Bart Nuttin; Bart Preneel (CODASPY, 2018)

Towards inter-vendor compatibility of true random number generators for FPGAs. - Milos Grujic; Bohan Yang 001; Vladimir Rozic; Ingrid Verbauwhede (DATE, 2018)

Design and testing methodologies for true random number generators towards industry certification. - Josep Balasch; Florent Bernard; Viktor Fischer; Milos Grujic; Marek Laban; Oto Petura; Vladimir Rozic; Gerard van Battum; Ingrid Verbauwhede; Marnix Wakker; Bohan Yang 001 (ETS, 2018)

The Impact of Pulsed Electromagnetic Fault Injection on True Random Number Generators. - Maxime Madau; Michel Agoyan; Josep Balasch; Milos Grujic; Patrick Haddad; Philippe Maurine; Vladimir Rozic; Dave Singelée; Bohan Yang 001; Ingrid Verbauwhede (FDTC, 2018)

A Closer Look at the Delay-Chain based TRNG. - Milos Grujic; Vladimir Rozic; Bohan Yang 001; Ingrid Verbauwhede (ISCAS, 2018)

ES-TRNG: A High-throughput, Low-area True Random Number Generator based on Edge Sampling. - Bohan Yang 001; Vladimir Rozic; Milos Grujic; Nele Mentens; Ingrid Verbauwhede (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018)

A High-performance Hardware Implementation of Saber Based on Karatsuba Algorithm. - Yihong Zhu; Min Zhu 001; Bohan Yang 001; Wenping Zhu; Chenchen Deng; Chen Chen 083; Shaojun Wei; Leibo Liu (IACR Cryptol. ePrint Arch., 2020)

Towards efficient and automated side-channel evaluations at design time. - Danilo Sijacic; Josep Balasch; Bohan Yang 001; Santosh Ghosh; Ingrid Verbauwhede (J. Cryptogr. Eng., 2020)

Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT. - Neng Zhang 002; Bohan Yang 001; Chen Chen 083; Shouyi Yin; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020)

Efficient Comparison and Addition for FHE With Weighted Computational Complexity Model. - Neng Zhang 002; Qiao Qin; Zongsheng Hou; Bohan Yang 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR. - Yihong Zhu; Min Zhu 001; Bohan Yang 001; Wenping Zhu; Chenchen Deng; Chen Chen 083; Shaojun Wei; Leibo Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Efficient access scheme for multi-bank based NTT architecture through conflict graph. - Xiangren Chen; Bohan Yang 001; Yong Lu; Shouyi Yin; Shaojun Wei; Leibo Liu (DAC, 2022)

A SHA-512 Hardware Implementation Based on Block RAM Storage Structure. - Mingyuan Yang; Yemeng Zhang; Bohan Yang 001; Hanning Wang; Shouyi Yin; Shaojun Wei; Leibo Liu (IPDPS Workshops, 2022)

An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance. - Chenchen Deng; Min Zhu 001; Jinjiang Yang; Youyu Wu; Jiaji He; Bohan Yang 001; Jianfeng Zhu 001; Shouyi Yin; Shaojun Wei; Leibo Liu (Sci. China Inf. Sci., 2022)

Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding. - Zongsheng Hou; Neng Zhang 002; Bohan Yang 001; Hanning Wang; Min Zhu 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme. - Xiangren Chen; Bohan Yang 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium. - Cankun Zhao; Neng Zhang 002; Hanning Wang; Bohan Yang 001; Wenping Zhu; Zhengdong Li; Min Zhu 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

A Low-Randomness First-Order Masked Xoodyak. - Shuohang Peng; Bohan Yang 001; Shuying Yin; Hang Zhao; Cankun Zhao; Shaojun Wei; Leibo Liu (HOST, 2023)

A Closer Look at the Chaotic Ring Oscillators based TRNG Design. - Shuqin Su; Bohan Yang 001; Vladimir Rozic; Mingyuan Yang; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023)

Sparse Polynomial Multiplication-Based High-Performance Hardware Implementation for CRYSTALS-Dilithium. - Hang Zhao; Cankun Zhao; Wenping Zhu; Bohan Yang 001; Shaojun Wei; Leibo Liu (HOST, 2024)

UpWB: An Uncoupled Architecture Design for White-box Cryptography Using Vectorized Montgomery Multiplication. - Xiangren Chen; Bohan Yang 001; Jianfeng Zhu 001; Jun Liu; Shuying Yin; Guang Yang; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

A Low-Latency High-Order Arithmetic to Boolean Masking Conversion. - Jiangxue Liu; Cankun Zhao; Shuohang Peng; Bohan Yang 001; Hang Zhao; Xiangdong Han; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

Breaking Ground: A New Area Record for Low-Latency First-Order Masked SHA-3 Advancing from the 4x Area Era to the 3x Area Era. - Cankun Zhao; Hang Zhao; Jiangxue Liu; Bohan Yang 001; Wenping Zhu; Shuying Yin; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

17.2 A 28nm 4.05µJ/Encryption 8.72kHMul/s Reconfigurable Multi-Scheme Fully Homomorphic Encryption Processor for Encrypted Client-Server Computing. - Sijia Lu; Wenping Zhu; Bohan Yang 001; Jiajun Yang; Tongwei Dai; Chen Chen 083; Xiangdong Han; Jinjiang Yang; Hanning Wang; Min Zhu 001; Shaojun Wei; Aoyang Zhang; et al. (ISSCC, 2025)

A High-performance NTT/MSM Accelerator for Zero-knowledge Proof Using Load-balanced Fully-pipelined Montgomery Multiplier. - Xiangren Chen; Bohan Yang 001; Wenping Zhu; Hanning Wang; Qichao Tao; Shuying Yin; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

On the Characterization of Phase Noise for the Robust and Resilient PLL-TRNG Design. - Ziheng Ma; Bohan Yang 001; Wenping Zhu; Hanning Wang; Yi Ouyang; Min Zhu 001; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

FalconSign: An Efficient and High-Throughput Hardware Architecture for Falcon Signature Generation. - Yi Ouyang; Yihong Zhu; Wenping Zhu; Bohan Yang 001; Zirui Zhang; Hanning Wang; Qichao Tao; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

A 28-nm Software-Defined Accelerator Chip With Circuit-Pipeline Scaling and Intrinsic Physical Unclonable Function Enabling Secure Configuration. - Jianfeng Zhu 001; Bohan Yang 001; Longlong Chen; Jinyi Chen; Yong Zhang; Liangwei Li; Liwei Zhang; Hanning Wang; Shaojun Wei; Leibo Liu (IEEE J. Solid State Circuits, 2025)