Hybrid high-performance low-power and ultra-low energy reliable caches. - Bojan Maric; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (Conf. Computing Frontiers, 2011)

ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches. - Bojan Maric; Jaume Abella 001; Mateo Valero (ACM Great Lakes Symposium on VLSI, 2012)

APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation. - Bojan Maric; Jaume Abella 001; Mateo Valero (DAC, 2013)

Efficient cache architectures for reliable hybrid voltage operation using EDC codes. - Bojan Maric; Jaume Abella 001; Mateo Valero (DATE, 2013)

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation. - Bojan Maric; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (ACM Trans. Design Autom. Electr. Syst., 2014)

Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes. - Bojan Maric; Jaume Abella 001; Mateo Valero (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Cache designs for reliable hybrid high and ultra-low voltage operation. - Bojan Maric (2014)

Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip. - David R. Ditzel; Roger Espasa; Nivard Aymerich; Allen Baum; Tom Berg; Jim Burr; Eric Hao; Jayesh Iyer; Miquel Izquierdo; Shankar Jayaratnam; Darren Jones; Chris Klingner; et al. (HCS, 2021)