A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM. - Changyoung Lee; Youngseok Park; Hyunchul Yoon; Seryeong Yoon; Donggeon Kim; Bokyeon Won; Junhwa Song; In-Jae Bae; Jaejoon Song; Kyuchang Kang; Jaehyuk Kim; Kyungrak Cho; et al. (A-SSCC, 2024)

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sanghoon Kim; Daewoong Lee; Seongyeal Yang; Gil-Young Kang; Juseop Park; Kyungho Lee; Hwan-Chul Jung; Gun-hee Cho; et al. (ISSCC, 2024)

An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM. - Kyeongtae Nam; Jaehyuk Kim; Dongil Lee; Kyuchang Kang; Sangyun Kim; Changyoung Lee; Hyunchul Yoon; Donggeon Kim; Bokyeon Won; Jaejoon Song; Incheol Nam; Young-Hun Seo; et al. (VLSI Technology and Circuits, 2024)

30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction. - Sang-Hoon Kim; Jaehyeok Baek; Moon-Chul Choi; Daewoong Lee; Donggun An; Se-Mi Kim; Yeonggeun Song; Minkyo Shim; Sung-Yong Cho; Dongha Lee; Gun-hee Cho; Inwoo Jun; et al. (ISSCC, 2025)

A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sang-Hoon Kim; Daewoong Lee; Seongyeal Yang; Se-Mi Kim; Gil-Young Kang; Juseop Park; Kyung-Ho Lee; Hwan-Chul Jung; et al. (IEEE J. Solid State Circuits, 2025)

An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier. - Kyeongtae Nam; Dongil Lee; Kyuchang Kang; Sangyun Kim; Changyoung Lee; Hyunchul Yoon; Donggeon Kim; Bokyeon Won; Jaejoon Song; Jaehyuk Kim; Incheol Nam; Young-Hun Seo; et al. (IEEE J. Solid State Circuits, 2025)