Using multi-channel priority scheduling mechanism to improve the transmission efficiency of Store-Forward processing structure under RISC-V architecture. - Boling Chen; Jiacheng Fu; Dengbin Liao; Junbing Pan; Xiaoying Mo; Yiting Huang (Informatica (Slovenia), 2026)

AssertMiner-pro: Enhanced module-level spec generation and assertion mining with LLM guided by top-down hierarchical strategies. - Yonghao Wang; Jiaxin Zhou; Hongqin Lyu; Boling Chen; Mingyu Shi; Zhiteng Chao; Tiancheng Wang; Huawei Li 001 (Integr., 2026)

From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation. - Yonghao Wang; Hongqin Lyu; Boling Chen; MinYang Bao; Wenchao Ding 007; Feng Gu; Zhiteng Chao; Jianan Mu; Kan Shi; Tiancheng Wang; Huawei Li 001 (CoRR, 2026)