Recent progresses of STT memory design and applications. - Bonan Yan; Yaojun Zhang; Enes Eken; Wujie Wen; Weisheng Zhao; Yiran Chen 001 (ASICON, 2015)

Spiking-based matrix computation by leveraging memristor crossbar array. - Hai (Helen) Li; Chenchen Liu; Bonan Yan; Chaofei Yang; Linghao Song; Zheng Li; Yiran Chen 001; Weijie Zhu; Qing Wu 002; Hao Jiang 014 (CISDA, 2015)

A spiking neuromorphic design with resistive crossbar. - Chenchen Liu; Bonan Yan; Chaofei Yang; Linghao Song; Zheng Li; Beiye Liu; Yiran Chen 001; Hai Li 001; Qing Wu 002; Hao Jiang 014 (DAC, 2015)

Giant spin hall effect (GSHE) logic design for low power application. - Yaojun Zhang; Bonan Yan; Wenqing Wu; Hai Li 001; Yiran Chen 001 (DATE, 2015)

A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback. - Bonan Yan; Zheng Li; Yaojun Zhang; Jianlei Yang 001; Hai Li 001; Weisheng Zhao; Pierre Chor-Fung Chia (ACM Great Lakes Symposium on VLSI, 2015)

A new self-reference sensing scheme for TLC MRAM. - Zheng Li; Bonan Yan; Lun Yang; Weisheng Zhao; Yiran Chen 001; Hai Li 001 (ISCAS, 2015)

An overview on memristor crossabr based neuromorphic circuit and architecture. - Zheng Li; Chenchen Liu; Yandan Wang; Bonan Yan; Chaofei Yang; Jianlei Yang 001; Hai Li 001 (VLSI-SoC, 2015)

A neuromorphic ASIC design using one-selector-one-memristor crossbar. - Bonan Yan; Amr Mahmoud Mahmoud; Jianhua Joshua Yang; Qing Wu 002; Yiran Chen 001; Hai (Helen) Li (ISCAS, 2016)

A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy. - Chenchen Liu; Qing Yang 011; Bonan Yan; Jianlei Yang 001; Xiaocong Du; Weijie Zhu; Hao Jiang 014; Qing Wu 002; Mark Barnell; Hai Li 001 (ISVLSI, 2016)

Spin-Hall Assisted STT-RAM Design and Discussion. - Enes Eken; Ismail Bayram; Yaojun Zhang; Bonan Yan; Wenqing Wu; Hai (Helen) Li; Yiran Chen 001 (SLIP, 2016)

Low-power neuromorphic speech recognition engine with coarse-grain sparsity. - Shunti Yin; Deepak Kadetotad; Bonan Yan; Chang Song 001; Yiran Chen 001; Chaitali Chakrabarti; Jae-sun Seo (ASP-DAC, 2017)

A closed-loop design to enhance weight stability of memristor based neural network chips. - Bonan Yan; Jianhua Joshua Yang; Qing Wu 002; Yiran Chen 001; Hai Li 001 (ICCAD, 2017)

Giant Spin-Hall assisted STT-RAM and logic design. - Enes Eken; Ismail Bayram; Yaojun Zhang; Bonan Yan; Wenqing Wu; Hai (Helen) Li; Yiran Chen 001 (Integr., 2017)

Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design. - Yaojun Zhang; Bonan Yan; Xiaobin Wang; Yiran Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

A neuromorphic design using chaotic mott memristor with relaxation oscillation. - Bonan Yan; Xiong Cao; Hai (Helen) Li (DAC, 2018)

Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices. - Bonan Yan; Fan Chen 001; Yaojun Zhang; Chang Song 001; Hai Li 001; Yiran Chen 001 (DATE, 2018)

Challenges of memristor based neuromorphic computing system. - Bonan Yan; Yiran Chen 001; Hai Li 001 (Sci. China Inf. Sci., 2018)

Build reliable and efficient neuromorphic design with memristor technology. - Bing Li 017; Bonan Yan; Chenchen Liu; Hai (Helen) Li (ASP-DAC, 2019)

An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive Applications. - Bing Li 017; Bonan Yan; Hai Li 001 (ACM Great Lakes Symposium on VLSI, 2019)

Hardware Fault Tolerance for Binary RRAM Crossbars. - Arjun Chaudhuri; Bonan Yan; Yiran Chen 001; Krishnendu Chakrabarty (ITC, 2019)

Resistive Memory-Based In-Memory Computing: From Device and Large-Scale Integration System Perspectives. - Bonan Yan; Bing Li 017; Ximing Qiao; Cheng-Xin Xue; Meng-Fan Chang; Yiran Chen 001; Hai Helen Li (Adv. Intell. Syst., 2019)

ReSiPE: ReRAM-based Single-Spiking Processing-In-Memory Engine. - Ziru Li; Bonan Yan; Hai Helen Li (DAC, 2020)

Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks. - Qilin Zheng; Zongwei Wang 001; Zishun Feng; Bonan Yan; Yimao Cai; Ru Huang 001; Yiran Chen 001; Chia-Lin Yang; Hai Helen Li (DAC, 2020)

ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration. - Xiaoxuan Yang 001; Bonan Yan; Hai Li 001; Yiran Chen 001 (ICCAD, 2020)

Highly Efficient Neuromorphic Computing Systems With Emerging Nonvolatile Memories. - Bonan Yan (2020)

Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT Applications. - Kangyi Qiu; Yaojun Zhang; Bonan Yan; Ru Huang 001 (ASP-DAC, 2022)

ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses. - Ziru Li; Qilin Zheng; Bonan Yan; Ru Huang 001; Bing Li 005; Yiran Chen 001 (DAC, 2022)

A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. - Bonan Yan; Jeng-Long Hsu; Pang-Cheng Yu; Chia-Chi Lee; Yaojun Zhang; Wenshuo Yue; Guoqiang Mei; Yuchao Yang 001; Yue Yang; Hai Li 001; Yiran Chen 001; Ru Huang 001 (ISSCC, 2022)

Memristive devices based hardware for unlabeled data processing. - Zhuojian Xiao; Bonan Yan; Teng Zhang; Ru Huang 001; Yuchao Yang 001 (Neuromorph. Comput. Eng., 2022)

VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators. - Zhaokun Jing; Bonan Yan; Yuchao Yang 001; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Live Demonstration: SRAM Compute-In-Memory Based Visual & Aural Recognition System. - Anjunyi Fan; Bo Hu; Zhonghua Jin; Haiyue Han; Yaojun Zhang; Yue Yang; Yuchao Yang 001; Bonan Yan; Ru Huang 001 (AICAS, 2023)

STAR: An Efficient Softmax Engine for Attention Model with RRAM Crossbar. - Yifeng Zhai; Bing Li; Bonan Yan; Jing Wang 055 (DATE, 2023)

Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search. - Lei Cai; Jing Wang 172; Lianfeng Yu; Bonan Yan; Yaoyu Tao; Yuchao Yang 001 (FPGA, 2023)

SRAM-Based Processing-In-Memory Design with Kullback-Leibler Divergence-Based Dynamic Precision Quantization. - Yanjun Li; Chunshan Zu; Bingqian Wang; Zhenhua Zhu; Yaojun Zhang; Ran Duan; Bing Li 017; Bonan Yan (ACM Great Lakes Symposium on VLSI, 2023)

Fast and reconfigurable sort-in-memory system enabled by memristors. - Lianfeng Yu; Yaoyu Tao; Teng Zhang; Zeyu Wang; Xile Wang; Zelun Pan; Bowen Wang; Zhaokun Jing; Jiaxin Liu; Yuqi Li; Yihang Zhu; Bonan Yan; et al. (CoRR, 2023)

Hadamard product-based in-memory computing design for floating point neural network training. - Anjunyi Fan; Yihan Fu; Yaoyu Tao; Zhonghua Jin; Haiyue Han; Huiyu Liu; Yaojun Zhang; Bonan Yan; Yuchao Yang 001; Ru Huang 001 (Neuromorph. Comput. Eng., 2023)

Memristive dynamics enabled neuromorphic computing systems. - Bonan Yan; Yuchao Yang 001; Ru Huang 001 (Sci. China Inf. Sci., 2023)

Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. - Cenlin Duan; Jianlei Yang 001; Yiou Wang; Yikun Wang; Yingjie Qi; Xiaolin He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weisheng Zhao (DAC, 2024)

MeMCISA: Memristor-Enabled Memory-Centric Instruction-Set Architecture for Database Workloads. - Yihang Zhu; Lei Cai; Lianfeng Yu; Anjunyi Fan; Longhao Yan; Zhaokun Jing; Bonan Yan; Pek Jun Tiw; Yuqi Li; Yaoyu Tao; Yuchao Yang 001 (MICRO, 2024)

AttentionLego: An Open-Source Building Block For Spatially-Scalable Large Language Model Accelerator With Processing-In-Memory Technology. - Rongqing Cong; Wenyang He; Mingxuan Li; Bangning Luo; Zebin Yang; Yuchao Yang 001; Ru Huang 001; Bonan Yan (CoRR, 2024)

Generalized Ping-Pong: Off-Chip Memory Bandwidth Centric Pipelining Strategy for Processing-In-Memory Accelerators. - Ruibao Wang; Bonan Yan (CoRR, 2024)

Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling. - Yihan Fu; Daijing Shi; Anjunyi Fan; Wenshuo Yue; Yuchao Yang 001; Ru Huang 001; Bonan Yan (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. - Cenlin Duan; Jianlei Yang 001; Xiaolin He; Yingjie Qi; Yikun Wang; Yiou Wang; Ziyan He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weitao Pan; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

PEARL: FPGA-Based Reinforcement Learning Acceleration with Pipelined Parallel Environments. - Jiayi Li; Hongxiao Zhao; Wenshuo Yue; Yihan Fu; Daijing Shi; Anjunyi Fan; Yuchao Yang; Bonan Yan (DATE, 2025)

PROCA: Programmable Probabilistic Processing Unit Architecture with Accept/Reject Prediction & Multicore Pipelining for Causal Inference. - Yihan Fu; Anjunyi Fan; Wenshuo Yue; Hongxiao Zhao; Daijing Shi; Qiuping Wu; Jiayi Li; Xiangyu Zhang; Yaoyu Tao; Yuchao Yang 001; Bonan Yan (HPCA, 2025)

A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array. - Ruiqi Guo; Zhiheng Yue; Yang Wang 089; Hao Li; Te Hu; Yabing Wang; Hao Sun; Jeng-Long Hsu; Yaojun Zhang; Bonan Yan; Leibo Liu; Ru Huang 001; et al. (IEEE J. Solid State Circuits, 2025)

Non-Binary LDPC Arithmetic Error Correction For Processing-in-Memory. - Daijing Shi; Yihang Zhu; Anjunyi Fan; Yaoyu Tao; Yuchao Yang 001; Bonan Yan (CoRR, 2025)

Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity. - Cenlin Duan; Jianlei Yang 001; Yikun Wang; Yiou Wang; Yingjie Qi; Xiaolin He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weisheng Zhao (CoRR, 2025)