Integration of silicon photonics into DRAM process. - Dongjae Shin; Kwansik Cho; Ho-Chul Ji; Beomsuk Lee; S. G. Kim; J. K. Bok; S. H. Choi; Yonghwack Shin; J. H. Kim; S. Y. Lee; K. Y. Cho; Bong Jin Kuh; et al. (OFC/NFOEC, 2013)

BOX-less waveguide Ge PD for bulk-Si based silicon photonic platform. - Ho-Chul Ji; Kwansik Cho; Beomsuk Lee; K. Y. Cho; S. H. Choi; J. H. Kim; Yonghwack Shin; S. G. Kim; S. Y. Lee; Hyunil Byun; S. Parmar; A. H. Nejadmalayeri; et al. (OFC, 2014)

Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM -. - Jung-Won Han; S. H. Park; Moonyoung Jeong; K. N. Kim; H. J. Kim; J. C. Shin; S. M. Park; S. H. Shin; S. W. Park; K. S. Lee; J. H. Lee; S. H. Kim; et al. (VLSI Technology and Circuits, 2023)

Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node. - Daewon Ha; Y. Lee; Shinjae Yoo; W. Lee; M. H. Cho; K. Yoo; S. M. Lee; S. Lee; M. Terai; T. H. Lee; J. H. Bae; K. J. Moon; et al. (IMW, 2024)

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET. - Taeyoung Kim; Suhwan Lim; Ilho Myeong; Sanghyun Park; Suseong Noh; Seung Min Lee; Jongho Woo; Hanseung Ko; Youngji Noh; Moonkang Choi; Kiheun Lee; Sangwoo Han; et al. (IRPS, 2024)

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND. - Ilho Myeong; Suhwan Lim; Taeyoung Kim; Sanghyun Park; Suseong Noh; Seung Min Lee; Jongho Woo; Hanseung Ko; Youngji Noh; Munkang Choi; Kiheun Lee; Sangwoo Han; et al. (IRPS, 2024)

Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch. - Jaehyun Park; Juhun Park; Kyuman Hwang; Jinchan Yun; Dahye Kim; Sungil Park; Jejune Park; Jinwook Yang; Jae Won Jeong; Chuljin Yun; Jinho Bae; Sam Park; et al. (VLSI Technology and Circuits, 2024)