A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit. - Sang-Hyun Lee; Moon-Sang Hwang; Youngdon Choi; Sungjoon Kim; Yongsam Moon; Bong-Joon Lee; Deog-Kyoon Jeong; Wonchan Kim; Young-June Park; Gijung Ahn (IEEE J. Solid State Circuits, 2002)

A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization. - Bong-Joon Lee; Moon-Sang Hwang; Sang-Hyun Lee; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2003)

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique. - Hyung-Rok Lee; Moon-Sang Hwang; Bong-Joon Lee; Young-Deok Kim; Dohwan Oh; Jaeha Kim; Sang-Hyun Lee; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2005)

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-μm CMOS. - Jaeha Kim; Jeong-Kyoum Kim; Bong-Joon Lee; Namhoon Kim; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2006)

A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme. - Won-Jun Choe; Bong-Joon Lee; Jaeha Kim; Deog-Kyoon Jeong; Gyudong Kim (IEEE J. Solid State Circuits, 2007)

Design Optimization of On-Chip Inductive Peaking Structures for 0.13-μm CMOS 40-Gb/s Transmitter Circuits. - Jaeha Kim; Jeong-Kyoum Kim; Bong-Joon Lee; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)