Integral transforms, convolution products, and first variations. - Bongjin Kim; Byoung Soo Kim; David L. Skoug (Int. J. Math. Math. Sci., 2004)

A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer. - Jongshin Shin; Jaehyun Park; Bongjin Kim; Jongjae Ryu; Chiwon Kim; Jiyoung Kim; Seung-Hee Yang; Hyungoo Kim; Jaewhui Kim (CICC, 2008)

Dual-rail decoding of low-density parity-check codes. - Bongjin Kim; Hasan Ahmed; In-Cheol Park (ISCAS, 2010)

QC-LDPC Decoding Architecture based on Stride Scheduling. - Bongjin Kim; In-Cheol Park (ISCAS, 2011)

Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. - Pingqiang Zhou; Won Ho Choi; Bongjin Kim; Chris H. Kim; Sachin S. Sapatnekar (ICCAD, 2012)

Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding. - Injae Yoo; Bongjin Kim; In-Cheol Park (IEEE Commun. Lett., 2012)

Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation. - Dong Jiao; Bongjin Kim; Chris H. Kim (IEEE J. Solid State Circuits, 2012)

A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal. - Bongjin Kim; Weichao Xu; Chris H. Kim (CICC, 2013)

Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes. - Injae Yoo; Bongjin Kim; In-Cheol Park (VTC Spring, 2013)

Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division. - Bongjin Kim; In-Cheol Park (IEICE Trans. Commun., 2013)

Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns. - Bongjin Kim; Injae Yoo; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals. - Bongjin Kim; Somnath Kundu; Seokkyun Ko; Chris H. Kim (CICC, 2014)

True Random Number Generator circuits based on single- and multi-phase beat frequency detection. - Qianying Tang; Bongjin Kim; Yingjie Lao; Keshab K. Parhi; Chris H. Kim (CICC, 2014)

A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter. - Bongjin Kim; Weichao Xu; Chris H. Kim (IEEE J. Solid State Circuits, 2014)

Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders. - Injae Yoo; Bongjin Kim; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes. - Byeong Yong Kong; Jihyuck Jo; Hyewon Jeong; Mina Hwang; Soyoung Cha; Bongjin Kim; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2014)

An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier. - Bongjin Kim; Hoon Ki Kim; Chris H. Kim (CICC, 2015)

Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals. - Somnath Kundu; Bongjin Kim; Chris H. Kim (CICC, 2015)

A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit. - Bongjin Kim; Somnath Kundu; Chris H. Kim (VLSIC, 2015)

Low-Complexity Tree Architecture for Finding the First Two Minima. - Youngjoo Lee; Bongjin Kim; Jaehwan Jung; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders. - Injae Yoo; Bongjin Kim; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection. - Somnath Kundu; Bongjin Kim; Chris H. Kim (ISSCC, 2016)

A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection. - Somnath Kundu; Bongjin Kim; Chris H. Kim (IEEE J. Solid State Circuits, 2017)

All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits. - Gyusung Park; Minsu Kim; Chris H. Kim; Bongjin Kim; Vijay Reddy (IRPS, 2018)

A 28Gb/s transceiver with chirp-managed EDC for DML systems. - Kyeongha Kwon; Jong-Hyeok Yoon; Hanho Choi; Younho Jeon; Jaehyeok Yang; Bongjin Kim; Soon-Won Kwon; Minsik Kim 004; Sejun Jeon; Hyosup Won; Hyeon-Min Bae (ISSCC, 2018)

A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC. - Hyunjoon Kim; Qian Chen 027; Bongjin Kim (A-SSCC, 2019)

A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation. - Hyunjoon Kim; Qian Chen 027; Taegeun Yoo; Tony Tae-Hyoung Kim; Bongjin Kim (ESSCIRC, 2019)

A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks. - Taegeun Yoo; Hyunjoon Kim; Qian Chen 027; Tony Tae-Hyoung Kim; Bongjin Kim (ISLPED, 2019)

A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks. - Hyunjoon Kim; Qian Chen 027; Taegeun Yoo; Tony Tae-Hyoung Kim; Bongjin Kim (ISOCC, 2019)

Mixed-Signal Circuits and Architectures for Energy-Efficient In-Memory and In-Sensor Computation of Artificial Neural Networks. - Bongjin Kim (SoCC, 2019)

A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC. - Chengshuo Yu; Taegeun Yoo; Tony Tae-Hyoung Kim; Kevin Tshun Chuan Chai; Bongjin Kim (CICC, 2020)

A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length. - Qian Chen 027; Yuqi Su; Hyunjoon Kim; Taegeun Yoo; Tony Tae-Hyoung Kim; Bongjin Kim (DATE, 2020)

A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter. - Qian Chen 027; Yuan Liang 004; Bongjin Kim; Chirn Chye Boon (ISCAS, 2020)

Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing. - Yuzong Chen 001; Lu Lu 013; Bongjin Kim; Tony Tae-Hyoung Kim (ISCAS, 2020)

A 65nm Logic-Compatible Embedded and Flash Memory for In-Memory Computation of Artificial Neural Networks. - Junjie Mu; Bongjin Kim (ISCAS, 2020)

Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks. - Taegeun Yoo; Tony Tae-Hyoung Kim; Bongjin Kim; Chengshuo Yu; Kevin Chai Tshun Chuan (ISOCC, 2020)

31.2 CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems. - Yuqi Su; Hyunjoon Kim; Bongjin Kim (ISSCC, 2020)

Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory. - Yuzong Chen 001; Lu Lu 013; Bongjin Kim; Tony Tae-Hyoung Kim (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems. - Yuqi Su; Junjie Mu; Hyunjoon Kim; Bongjin Kim (CICC, 2021)

A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations. - Chengshuo Yu; Yuqi Su; Jaeho Lee; Kevin T. C. Chai; Bongjin Kim (CICC, 2021)

A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC. - Chengshuo Yu; Kevin Tshun Chuan Chai; Tony Tae-Hyoung Kim; Bongjin Kim (ESSDERC, 2021)

A 21×21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method. - Junjie Mu; Bongjin Kim (ISSCC, 2021)

A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems. - Junjie Mu; Yuqi Su; Bongjin Kim (VLSI Circuits, 2021)

Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks. - Hyunjoon Kim; Taegeun Yoo; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2021)

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications. - Yuzong Chen 001; Lu Lu 013; Bongjin Kim; Tony Tae-Hyoung Kim (IEEE Open J. Circuits Syst., 2021)

A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks. - Chengshuo Yu; Taegeun Yoo; Hyunjoon Kim; Tony Tae-Hyoung Kim; Kevin Chai Tshun Chuan; Bongjin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method. - Junjie Mu; Chengshuo Yu; Tony Tae-Hyoung Kim; Bongjin Kim (ESSCIRC, 2022)

FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems. - Yuqi Su; Tony Tae-Hyoung Kim; Bongjin Kim (ISSCC, 2022)

A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. - Fengbin Tu; Yiqi Wang 005; Zihan Wu 006; Ling Liang; Yufei Ding 001; Bongjin Kim; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (ISSCC, 2022)

Guest Editorial Revolution of AI and Machine Learning With Processing-in-Memory (PIM): From Systems, Architectures, to Circuits. - Tony Tae-Hyoung Kim; Bongjin Kim; Joo-Young Kim 001; Jaydeep P. Kulkarni (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning. - Donghyuk Kim; Chengshuo Yu; Shanshan Xie; Yuzong Chen 001; Joo-Young Kim 001; Bongjin Kim; Jaydeep P. Kulkarni; Tony Tae-Hyoung Kim (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems. - Yuqi Su; Hyunjoon Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2022)

A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems. - Yuqi Su; Junjie Mu; Hyunjoon Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2022)

A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks. - Chengshuo Yu; Taegeun Yoo; Kevin Tshun Chuan Chai; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2022)

SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks. - Junjie Mu; Hyunjoon Kim; Bongjin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Reconfigurable lsing Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions. - Yuqi Su; Tony Tae-Hyoung Kim; Bongjin Kim (CICC, 2023)

A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates. - Chengshuo Yu; Junjie Mu; Kevin Tshun-Chuan Chai; Tony T. Kim; Bongjin Kim (CICC, 2023)

A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing. - Zhengzhe Wei; Junjie Mu; Zhongzhiguang Lu; Yuanjin Zheng; Tony Tae-Hyoung Kim; Bongjin Kim (ISCAS, 2023)

282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing. - Qibang Zang; Wang Ling Goh; Lu Lu 013; Chengshuo Yu; Junjie Mu; Tony Tae-Hyoung Kim; Bongjin Kim; Dongrui Li; Anh Tuan Do (ISCAS, 2023)

CTLE-Ising:A 1440-Spin Continuous-Time Latch-Based isling Machine with One-Shot Fully-Parallel Spin Updates Featuring Equalization of Spin States. - Jooyoung Bae; Wonsik Oh; Jahyun Koo 003; Bongjin Kim (ISSCC, 2023)

A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations. - Junjie Mu; Chengshuo Yu; Tony Tae-Hyoung Kim; Bongjin Kim (VLSI Technology and Circuits, 2023)

ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. - Fengbin Tu; Yiqi Wang 005; Zihan Wu 006; Ling Liang; Yufei Ding 001; Bongjin Kim; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (IEEE J. Solid State Circuits, 2023)

A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array. - Chengshuo Yu; Junjie Mu; Yuqi Su; Kevin Tshun Chuan Chai; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2023)

A Dynamic-Precision Bit-Serial Computing Hardware Accelerator for Solving Partial Differential Equations Using Finite Difference Method. - Junjie Mu; Bongjin Kim (IEEE J. Solid State Circuits, 2023)

A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks. - Hyunjoon Kim; Junjie Mu; Chengshuo Yu; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

ROC-Spin: A 28nm 2, 000 Ring-Oscillator-Collapse Spins for Solving Combinatorial Optimization Problems. - Yuqi Su; Anh Tuan Do; Tony Tae-Hyoung Kim; Bongjin Kim (A-SSCC, 2024)

15.5 LISA: A 576×4 All-in-One Replica-Spins Continuous-Time Latch-Based Ising Computer Using Massively-Parallel Random-Number Generations and Replica Equalizations. - Jooyoung Bae; Jahyun Koo 003; Chaeyun Shim; Bongjin Kim (ISSCC, 2024)

15.6 e-Chimera: A Scalable SRAM-Based Ising Macro with Enhanced-Chimera Topology for Solving Combinatorial Optimization Problems Within Memory. - Jooyoung Bae; Chaeyun Shim; Bongjin Kim (ISSCC, 2024)

30.3 VIP-Sat: A Boolean Satisfiability Solver Featuring 5×12 Variable In-Memory Processing Elements with 98% Solvability for 50-Variables 218-Clauses 3-SAT Problems. - Chaeyun Shim; Jooyoung Bae; Bongjin Kim (ISSCC, 2024)

Quantized Context Based LIF Neurons for Recurrent Spiking Neural Networks in 45nm. - Sai Sukruth Bezugam; Yihao Wu; JaeBum Yoo; Dmitri B. Strukov; Bongjin Kim (NICE, 2024)

CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully Parallel Spin Updates and Equalization of Spin States. - Jooyoung Bae; Wonsik Oh; Jahyun Koo 003; Chengshuo Yu; Bongjin Kim (IEEE J. Solid State Circuits, 2024)

A 26-Gb/s Framed-Pulsewidth Modulation Transceiver for Extended Reach Optical Links. - Woohyun Kwon; Hyosup Won; Taeho Kim; Sejun Jeon; Soon-Won Kwon; Ha-Il Song; Hanho Choi; Bongjin Kim; Huxian Jin; Jun-Gi Jo; Woosang Han; Tai-Young Kim; et al. (IEEE J. Solid State Circuits, 2024)

A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations. - Junjie Mu; Chengshuo Yu; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2024)

FlexSpin: A CMOS Ising Machine With 256 Flexible Spin Processing Elements With 8-b Coefficients for Solving Combinatorial Optimization Problems. - Yuqi Su; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE J. Solid State Circuits, 2024)

A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks. - Chengshuo Yu; Haoge Jiang; Junjie Mu; Kevin Tshun Chuan Chai; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Graph-Based Accelerator of Retinex Model With Bit-Serial Computing for Image Enhancements. - Zhengzhe Wei; Junjie Mu; Yuanjin Zheng; Tony Tae-Hyoung Kim; Bongjin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)