Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process. - John Turner; Richard Cliff; W. Leong; Cameron McClintock; Ninh Ngo; Khai Nguyen; Chiakang Sung; Bonnie Wang; J. Watson (FPL, 1995)

A silicon efficient FLEX 6000 programmable logic architecture. - Chiakang Sung; Richard Cliff; Joseph Huang; Bonnie Wang; Khai Nguyen; Xtaobao Wang; Kerry Veenstra; Bruce Pedersen; John Turner (CICC, 1998)

A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface. - Jeffrey Tyhach; Bonnie Wang; Chiakang Sung; Joseph Huang; Khai Nguyen; Xiaobao Wang; Yan Chong; Philip Pan; Henry Kim; Gopinath Rangan; Tzung-Chin Chang; Johnson Tan (CICC, 2004)

A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface. - Jeffrey Tyhach; Bonnie Wang; Chiakang Sung; Joseph Huang; Khai Nguyen; Xiaobao Wang; Yan Chong; Philip Pan; Henry Kim; Gopinath Rangan; Tzung-Chin Chang; Johnson Tan (IEEE J. Solid State Circuits, 2005)

Annotated-skeleton Biased Motion Planning for Faster Relevant Region Discovery. - Diane Uwacu; Regina Rex; Bonnie Wang; Shawna L. Thomas; Nancy M. Amato (CoRR, 2020)