Crossbar array of selector-less TaOx/TiO2 bilayer RRAM. - Chun-Tse Chou; Boris Hudec; Chung-Wei Hsu; Wei-Li Lai; Chih-Cheng Chang; Tuo-Hung Hou (Microelectron. Reliab., 2015)

3D resistive RAM cell design for high-density storage class memory - a review. - Boris Hudec; Chung-Wei Hsu; I-Ting Wang; Wei-Li Lai; Che-Chia Chang; Taifang Wang; Karol Fröhlich; Chia-Hua Ho; Chen-Hsi Lin; Tuo-Hung Hou (Sci. China Inf. Sci., 2016)

SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices. - Sandeep Kaur Kingra; Vivek Parmar; Che-Chia Chang; Boris Hudec; Tuo-Hung Hou; Manan Suri (CoRR, 2018)

Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse. - Chih-Cheng Chang; Pin-Chun Chen; Teyuh Chou; I-Ting Wang; Boris Hudec; Che-Chia Chang; Chia-Ming Tsai; Tian-Sheuan Chang; Tuo-Hung Hou (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar. - Sandeep Kaur Kingra; Vivek Parmar; Shubham Negi; Sufyan Khan; Boris Hudec; Tuo-Hung Hou; Manan Suri (ISCAS, 2020)