UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction. - Laung-Terng Wang; Khader S. Abdel-Hafez; Xiaoqing Wen; Boryau Sheu; Shianling Wu; Shyh-Horng Lin; Ming-Tung Chang (ITC, 2005)

Test compression and logic BIST at your fingertips. - Shianling Wu; Laung-Terng Wang; Jin Woo Cho; Zhigang Jiang; Boryau Sheu (ITC, 2005)

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing. - Hiroshi Furukawa; Xiaoqing Wen; Laung-Terng Wang; Boryau Sheu; Zhigang Jiang; Shianling Wu (ITC, 2006)

Practical Challenges in Logic BIST Implementation. - Shianling Wu; Hiroshi Furukawa; Boryau Sheu; Laung-Terng Wang; Hao-Jan Chao; Lizhen Yu; Xiaoqing Wen; Michio Murakami (ATS, 2008)

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. - Shianling Wu; Laung-Terng Wang; Zhigang Jiang; Jiayong Song; Boryau Sheu; Xiaoqing Wen; Michael S. Hsiao; James Chien-Mo Li; Jiun-Lang Huang; Ravi Apte (DFT, 2008)

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. - Laung-Terng Wang; Ravi Apte; Shianling Wu; Boryau Sheu; Kuen-Jong Lee; Xiaoqing Wen; Wen-Ben Jone; Chia-Hsien Yeh; Wei-Shin Wang; Hao-Jan Chao; Jianghao Guo; Jinsong Liu; et al. (ITC, 2008)

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. - Laung-Terng Wang; Xiaoqing Wen; Shianling Wu; Zhigang Wang; Zhigang Jiang; Boryau Sheu; Xinli Gu (IEEE Des. Test Comput., 2008)

Turbo1500: Core-Based Design for Test and Diagnosis. - Laung-Terng Wang; Ravi Apte; Shianling Wu; Boryau Sheu; Wen-Ben Jone; Jianghao Guo; Kuen-Jong Lee; Wei-Shin Wang; Xiaoqing Wen; Hao-Jan Chao; Jinsong Liu; Yanlong Niu; et al. (IEEE Des. Test Comput., 2009)

Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs. - Lizhen Yu; Jeffrey Hung; Boryau Sheu; Bill Huynh; Loc Nguyen; Shianling Wu; Laung-Terng Wang; Xiaoqing Wen (DFT, 2010)

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains. - Laung-Terng Wang; Xiaoqing Wen; Shianling Wu; Hiroshi Furukawa; Hao-Jan Chao; Boryau Sheu; Jianghao Guo; Wen-Ben Jone (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)