A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects. - Nan Qi; Yuhang Kang; Qipeng Lin; Jianxu Ma; Jingbo Shi; Bozhi Yin; Chang Liu; Rui Bai 001; Shang Hu; Juncheng Wang; Jiangbing Du; Lin Ma 008; et al. (A-SSCC, 2017)

A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS. - Juncheng Wang; Xuefeng Chen 004; Shang Hu; Yaxin Cai; Rui Bai 001; Xin Wang 130; Yuanxi Zhang; Shenglong Zhuo; Chang Liu; Bozhi Yin; Jianxu Ma; Hao Yan; et al. (A-SSCC, 2018)

A 50Gb/s-PAM4 CDR with On-Chip Eye Opening Monitor for Reference-Level and Clock-Sampling Adaptation. - Chang Liu; Bozhi Yin; Tingyu Yao; Nan Qi; Dan Li 011; Jingbo Shi; Juncheng Wang; Hu Shang; Rui Bai 001; Patrick Yin Chiang (OFC, 2018)

A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die. - Shang Hu; Tingyu Yao; Bozhi Yin; Chunyu Song; Lei Zhao; Juncheng Wang; Lei Wang 187; Rui Bai 001; Xin Wang 130; Tao Xia; Yi Peng; Binbin Yao; et al. (OFC, 2019)

A Laser-forwarded Coherent 10Gb/s BPSK Transceiver using Monolithic Microring Resonators in 45nm SOI CMOS. - Nandish Mehta; Sen Lin 002; Bozhi Yin; Sajjad Moazeni; Vladimir Stojanovic (VLSI Circuits, 2019)

A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS. - Qiwen Liao; Nan Qi; Miaofeng Li; Shang Hu; Jian He; Bozhi Yin; Jingbo Shi; Jian Liu 021; Patrick Yin Chiang; Xi Xiao; Nanjian Wu (IEEE J. Solid State Circuits, 2020)

A Laser-Forwarded Coherent Transceiver in 45-nm SOI CMOS Using Monolithic Microring Resonators. - Nandish Mehta; Sen Lin 002; Bozhi Yin; Sajjad Moazeni; Vladimir Stojanovic (IEEE J. Solid State Circuits, 2020)

Electronic-Photonic Cryogenic Egress Link. - Bozhi Yin; Hayk Gevorgyan; Deniz Onural; Anatol Khilo; Milos A. Popovic; Vladimir Marko Stojanovic (ESSDERC, 2021)

Cryo-Compatible, Silicon Spoked-Ring Modulator in a 45nm CMOS Platform for 4K-to-Room-Temperature Optical Links. - Hayk Gevorgyan; Anatol Khilo; Derek Van Orden; Deniz Onural; Bozhi Yin; Mark T. Wade; Vladimir Marko Stojanovic; Milos A. Popovic (OFC, 2021)

A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow. - Zhongkai Wang; Minsoo Choi 002; John Charles Wright; Kyoungtae Lee; Zhaokai Liu; Bozhi Yin; Jaeduk Han; Sijun Du; Elad Alon (ISCAS, 2022)

A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. - Zhongkai Wang; Minsoo Choi 002; Paul Kwon; Kyoungtae Lee; Bozhi Yin; Zhaokai Liu; Kwanseo Park; Ayan Biswas; Jaeduk Han; Sijun Du; Elad Alon (VLSI Technology and Circuits, 2022)

A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS. - Zhongkai Wang; Minsoo Choi 002; Paul Kwon; Zhaokai Liu; Bozhi Yin; Kyoungtae Lee; Kwanseo Park; Ayan Biswas; Jaeduk Han; Sijun Du; Elad Alon (ISCAS, 2024)

Cryogenic Optical Link: Device, Circuit, and System - Bozhi Yin (2024)