8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range. - Keith A. Bowman; Sarthak Raina; Todd Bridges; Daniel Yingling; Hoan Nguyen; Brad Appel; Yesh Kolla; Jihoon Jeong; Francois Atallah; David Hansquine (ISSCC, 2015)

A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range. - Keith A. Bowman; Sarthak Raina; Todd Bridges; Daniel Yingling; Hoan Nguyen; Brad Appel; Yesh Kolla; Jihoon Jeong; Francois Atallah; David Hansquine (IEEE J. Solid State Circuits, 2016)

A 7NM Double-Pumped 6R6W Register File for Machine Learning Memory. - Hoan Nguyen; Jihoon Jeong; Francois Atallah; Marc Jansen; Anthony Polomik; Daniel Yingling; Harsha Akkaraju; Brad Appel; Rahul Nadkarni; Keith A. Bowman (VLSI Circuits, 2018)

A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors. - Francois Atallah; Keith A. Bowman; Hoan Nguyen; Jihoon Jeong; Daniel Yingling; Yu Sun; Brad Appel; Anthony Polomik; Mahesh Harinath; Joshua Morelli; Thomas Moore; Nathaniel Reeves; et al. (ISSCC, 2019)

A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction. - Keith A. Bowman; Samantak Gangopadhyay; Francois Atallah; Hoan Nguyen; Jihoon Jeong; Daniel Yingling; Anthony Polomik; Mahesh Harinath; Nathaniel Reeves; Amer Cassier; Brad Appel; Arijit Raychowdhury (VLSI Circuits, 2019)