Accurate on-chip interconnect evaluation: a time-domain technique. - Krishnamurthy Soumyanath; Shekhar Borkar; Chunyan Zhou; Bradley A. Bloechel (IEEE J. Solid State Circuits, 1999)

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. - Ali Keshavarzi; Sean Ma; Siva G. Narendra; Brad Bloechel; K. Mistry; Tahir Ghani; Shekhar Borkar; Vivek De (ISLPED, 2001)

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. - Sriram R. Vangal; Mark A. Anders 001; Nitin Borkar; Erik Seligman; Venkatesh Govindarajulu; Vasantha Erraguntla; Howard Wilson; Amaresh Pangal; Venkat Veeramachaneni; James W. Tschanz; Yibin Ye; Dinesh Somasekhar; et al. (IEEE J. Solid State Circuits, 2002)

Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. - Peter Hazucha; Tanay Kamik; Steven Walstra; Bradley A. Bloechel; James W. Tschanz; Jose Maiz; Krishnamurthy Soumyanath; Greg Dermer; Siva G. Narendra; Vivek De; Shekhar Borkar (CICC, 2003)

17GHz and 24GHz LNA designs based on extended-S-parameter with microstrip-on-die in 0.18μm logic CMOS technology. - Luiz M. Franca-Neto; Bradley A. Bloechel; Krishnamurthy Soumyanath (ESSCIRC, 2003)

CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing. - Bartomeu Alorda; Brad Bloechel; Ali Keshavarzi; Jaume Segura 001 (ITC, 2003)

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. - Yatin Vasant Hoskote; Bradley A. Bloechel; Gregory E. Dermer; Vasantha Erraguntla; David Finan; Jason Howard; Dan Klowden; Siva G. Narendra; Greg Ruhl; James W. Tschanz; Sriram R. Vangal; Venkat Veeramachaneni; et al. (IEEE J. Solid State Circuits, 2003)

Forward body bias for microprocessors in 130-nm technology generation and beyond. - Siva G. Narendra; Ali Keshavarzi; Bradley A. Bloechel; Shekhar Borkar; Vivek De (IEEE J. Solid State Circuits, 2003)

Dynamic sleep transistor and body bias for active leakage power control of microprocessors. - James W. Tschanz; Siva G. Narendra; Yibin Ye; Bradley A. Bloechel; Shekhar Borkar; Vivek De (IEEE J. Solid State Circuits, 2003)

Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. - Peter Hazucha; Tanay Karnik; Steven Walstra; Bradley A. Bloechel; James W. Tschanz; Jose Maiz; Krishnamurthy Soumyanath; Gregory E. Dermer; Siva G. Narendra; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2004)

A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. - Dinesh Somasekhar; Shih-Lien Lu; Bradley A. Bloechel; Greg Dermer; Konrad Lai; Sjeljar Borkar; Vivek De (ESSCIRC, 2005)

Area-efficient linear regulator with ultra-fast load regulation. - Peter Hazucha; Tanay Karnik; Bradley A. Bloechel; Colleen Parsons; David Finan; Shekhar Borkar (IEEE J. Solid State Circuits, 2005)

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. - Peter Hazucha; Gerhard Schrom; Jaehong Hahn; Bradley A. Bloechel; Paul Hack; Gregory E. Dermer; Siva G. Narendra; Donald S. Gardner; Tanay Karnik; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2005)

A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS. - Sanu K. Mathew; Mark A. Anders 001; Brad Bloechel; Trang Nguyen; Ram K. Krishnamurthy; Shekhar Borkar (IEEE J. Solid State Circuits, 2005)