The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor. - Silvia M. Müller; Christian Jacobi 002; Hwa-Joon Oh; Kevin D. Tran; Scott R. Cottier; Brad W. Michael; Hiroo Nishikawa; Yonetaro Totsuka; Tatsuya Namatame; Naoka Yano; Takashi Machida; Sang H. Dhong (IEEE Symposium on Computer Arithmetic, 2005)

An SPU reference model for simulation, random test generation and verification. - Yukio Watanabe; Balazs Sallay; Brad W. Michael; Daniel A. Brokenshire; Gavin Meil; Hazim Shafi; Daisuke Hiraoka (ASP-DAC, 2006)

The microarchitecture of the synergistic processor for a cell processor. - Brian K. Flachs; Shigehiro Asano; Sang H. Dhong; H. Peter Hofstee; Gilles Gervais; Roy Kim; Tien Le; Peichun Liu; Jens Leenstra; John S. Liberty; Brad W. Michael; Hwa-Joon Oh; et al. (IEEE J. Solid State Circuits, 2006)

A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor. - Hwa-Joon Oh; Silvia M. Müller; Christian Jacobi 002; Kevin D. Tran; Scott R. Cottier; Brad W. Michael; Hiroo Nishikawa; Yonetaro Totsuka; Tatsuya Namatame; Naoka Yano; Takashi Machida; Sang H. Dhong (IEEE J. Solid State Circuits, 2006)

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. - Brian K. Flachs; Shigehiro Asano; Sang H. Dhong; H. Peter Hofstee; Gilles Gervais; Roy Kim; Tien Le; Peichun Liu; Jens Leenstra; John S. Liberty; Brad W. Michael; Hwa-Joon Oh; et al. (IBM J. Res. Dev., 2007)

IBM POWER9 memory architectures for optimized systems. - William J. Starke; J. S. Dodson; Jeffrey Stuecheli; Eric Retter; Brad W. Michael; Stephen J. Powell; James A. Marcella (IBM J. Res. Dev., 2018)