Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs. - Bradley F. Dutton; Charles E. Stroud (CATA, 2009)

Embedded Processor Based Fault Injection and SEU Emulation for FPGAs. - Bradley F. Dutton; Mustafa Ali; Charles E. Stroud; John Sunwoo (ESA, 2009)

Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs. - Bradley F. Dutton; Charles E. Stroud (ESA, 2009)

Soft Core Embedded Processor Based Built-In Self-Test of FPGAs. - Bradley F. Dutton; Charles E. Stroud (DFT, 2009)

Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems. - George J. Starr; Jie Qin; Bradley F. Dutton; Charles E. Stroud; Foster F. Dai; Victor P. Nelson (DFT, 2009)

The First Clock Cycle Is A Real BIST. - Charles E. Stroud; Bradley F. Dutton (ESA, 2010)

On-Line Single Event Upset Detection and Correction in Field Programmable Gate Array Configuration Memories. - Bradley F. Dutton; Charles E. Stroud (Int. J. Comput. Their Appl., 2010)

Selective Spectrum Analysis for Analog Measurements. - Jie Qin; Joseph Cali; Bradley F. Dutton; George J. Starr; Fa Foster Dai; Charles E. Stroud (IEEE Trans. Ind. Electron., 2011)