A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor. - Bradley J. Benschneider; William J. Bowhill; Elizabeth M. Copper; Moshe Gavrielov; Paul E. Gronowski; Vijay K. Maheshwari; Victor Peng; Jeffrey D. Pickholtz; Sridhar Samudrala (IEEE J. Solid State Circuits, 1989)

Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU - William J. Bowhill; Shane L. Bell; Bradley J. Benschneider; Andrew J. Black; Sharon M. Britton; Ruben W. Castelino; Dale R. Donchin; John H. Edmondson; Harry R. Fair III; Paul E. Gronowski; Anil K. Jain 003; Patricia L. Kroesen; et al. (Digit. Tech. J., 1995)

Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor - John H. Edmondson; Paul I. Rubinfeld; Peter J. Bannon; Bradley J. Benschneider; Debra Bernstein; Ruben W. Castelino; Elizabeth M. Cooper; Daniel E. Dever; Dale R. Donchin; Timothy C. Fischer; Anil K. Jain 003; Shekhar Mehta; et al. (Digit. Tech. J., 1995)

A 300-MHz 64-b quad-issue CMOS RISC microprocessor. - Bradley J. Benschneider; Andrew J. Black; William J. Bowhill; Sharon M. Britton; Daniel E. Dever; Dale R. Donchin; Robert J. Dupcak; Richard M. Fromm; Mary K. Gowan; Paul E. Gronowski; Michael Kantrowitz; Marc E. Lamere; et al. (IEEE J. Solid State Circuits, 1995)

Clocking design and analysis for a 600-MHz Alpha microprocessor. - Daniel W. Bailey; Bradley J. Benschneider (IEEE J. Solid State Circuits, 1998)