A CMOS transconductance-C filter technique for very high frequencies. - Bram Nauta (IEEE J. Solid State Circuits, 1992)

A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter. - Bram Nauta; Ardie G. Venes (IEEE J. Solid State Circuits, 1995)

A CMOS "soft-switched" transconductor and its application in gain control and filters. - Clemens H. J. Mensink; Bram Nauta; Hans Wallinga (IEEE J. Solid State Circuits, 1997)

Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology. - Gerrit W. den Besten; Bram Nauta (IEEE J. Solid State Circuits, 1998)

Guest Editorial. - Alain Guyot; Bram Nauta (IEEE J. Solid State Circuits, 1998)

Analog line driver with adaptive impedance matching. - Bram Nauta; Marcel B. Dijkstra (IEEE J. Solid State Circuits, 1998)

Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators. - Sander L. J. Gierkink; Eric A. M. Klumperink; Arnoud P. van der Wel; Gian Hoogzaad; Ed A. J. M. van Tuijl; Bram Nauta (IEEE J. Solid State Circuits, 1999)

Reducing MOSFET 1/f noise and power consumption by switched biasing. - Eric A. M. Klumperink; Sander L. J. Gierkink; Arnoud P. van der Wel; Bram Nauta (IEEE J. Solid State Circuits, 2000)

Finding all elementary circuits exploiting transconductance. - Eric A. M. Klumperink; Federico Bruccoleri; Bram Nauta (ISCAS (1), 2001)

Generating all two-MOS-transistor amplifiers leads to new wide-band LNAs. - Federico Bruccoleri; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2001)

Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). - Stefan Rusu; Manoj Sachdev; Christer Svensson; Bram Nauta (ASP-DAC/VLSI Design, 2002)

Systematic comparison of HF CMOS transconductors. - Eric A. M. Klumperink; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A wideband high-linearity RF receiver front-end in CMOS. - Vincent J. Arkesteijn; Eric A. M. Klumperink; Bram Nauta (ESSCIRC, 2004)

A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]. - Simon M. Louwsma; Ed J. M. van Tuijl; Maarten Vertregt; Peter C. S. Scholtens; Bram Nauta (ESSCIRC, 2004)

Distortion cancellation via polyphase multipath circuits. - Eisse Mensink; Eric A. M. Klumperink; Bram Nauta (ISCAS (1), 2004)

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS. - Remco C. H. van de Beek; Cicero S. Vaucher; Domine M. W. Leenaerts; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2004)

Wide-band CMOS low-noise amplifier exploiting thermal noise canceling. - Federico Bruccoleri; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2004)

A CMOS switched transconductor mixer. - Eric A. M. Klumperink; Simon M. Louwsma; Gerard J. M. Wienk; Bram Nauta (IEEE J. Solid State Circuits, 2004)

A robust 43-GHz VCO in CMOS for OC-768 SONET applications. - Arnoud P. van der Wel; Sander L. J. Gierkink; Robert C. Frye; Vito Boccuzzi; Bram Nauta (IEEE J. Solid State Circuits, 2004)

An audio FIR-DAC in a BCD process for high power class-D amplifiers. - T. S. Doorn; Ed van Tuijl; Daniël Schinkel; Anne-Johan Annema; Marco Berkhout; Bram Nauta (ESSCIRC, 2005)

Optimally-placed twists in global on-chip differential interconnects. - Eisse Mensink; Daniël Schinkel; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (ESSCIRC, 2005)

Analog/RF circuit design techniques for nanometerscale IC technologies. - Bram Nauta; Anne-Johan Annema (ESSCIRC, 2005)

Jitter limitations on multi-carrier modulation. - Jan H. Rutger Schrader; Eric A. M. Klumperink; Jan L. Visschers; Bram Nauta (ISCAS (6), 2005)

Analog circuits in ultra-deep-submicron CMOS. - Anne-Johan Annema; Bram Nauta; Ronald van Langevelde; Hans Tuinhout (IEEE J. Solid State Circuits, 2005)

A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication. - Sasa Radovanovic; Anne-Johan Annema; Bram Nauta (IEEE J. Solid State Circuits, 2005)

Bandwidth of integrated photodiodes in standard CMOS for CD/DVD applications. - Sasa Radovanovic; Anne-Johan Annema; Bram Nauta (Microelectron. Reliab., 2005)

Distortion cancellation by polyphase multipath circuits. - Eisse Mensink; Eric A. M. Klumperink; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Wireline Equalization using Pulse-Width Modulation. - Jan H. Rutger Schrader; Eric A. M. Klumperink; Jan L. Visschers; Bram Nauta (CICC, 2006)

Generalized Analytical Design Equations for Variable Slope Class-E Power Amplifiers. - Mustafa Acar; Anne-Johan Annema; Bram Nauta (ICECS, 2006)

Slew rate induced distortion in switched-resistor integrators. - Amorn Jiraseree-amornkun; Apisak Worapishet; Eric A. M. Klumperink; Bram Nauta; Wanlop Surakampontorn (ISCAS, 2006)

A multipath technique for canceling harmonics and sidebands in a wideband power upconverter. - Rameswor Shrestha; Eisse Mensink; Eric A. M. Klumperink; Gerard J. M. Wienk; Bram Nauta (ISSCC, 2006)

A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects. - Daniël Schinkel; Eisse Mensink; Eric A. M. Klumperink; Ed J. M. van Tuijl; Bram Nauta (IEEE J. Solid State Circuits, 2006)

Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb/s in 0.13-μm CMOS. - Jan H. Rutger Schrader; Eric A. M. Klumperink; Jan L. Visschers; Bram Nauta (IEEE J. Solid State Circuits, 2006)

A Polyphase Multipath Technique for Software-Defined Radio Transmitters. - Rameswor Shrestha; Eric A. M. Klumperink; Eisse Mensink; Gerard J. M. Wienk; Bram Nauta (IEEE J. Solid State Circuits, 2006)

Jitter requirements of the sampling clock in software radio receivers. - Vincent J. Arkesteijn; Eric A. M. Klumperink; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR. - Simon M. Louwsma; Ed van Tuijl; Maarten Vertregt; Bram Nauta (CICC, 2007)

An inductorless wideband balun-LNA in 65nm CMOS with balanced output. - Stephan C. Blaakmeer; Eric A. M. Klumperink; Bram Nauta; Domine M. W. Leenaerts (ESSCIRC, 2007)

Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance. - Mustafa Acar; Anne-Johan Annema; Bram Nauta (ISCAS, 2007)

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers. - Xiang Gao 002; Eric A. M. Klumperink; Bram Nauta (ISCAS, 2007)

Multipath Polyphase Circuits and their Application to RF Transceivers. - Eric A. M. Klumperink; Rameswor Shrestha; Eisse Mensink; Gerard Wienk; Zhiyu Ru; Bram Nauta (ISCAS, 2007)

On the Suitability of Discrete-Time Receivers for Software-Defined Radio. - Zhiyu Ru; Eric A. M. Klumperink; Bram Nauta (ISCAS, 2007)

Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS. - Ian Galton; Matt Miller; Robert Bogdan Staszewski; Bram Nauta; Michiel Steyaert (ISSCC, 2007)

A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects. - Eisse Mensink; Daniël Schinkel; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (ISSCC, 2007)

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time. - Daniël Schinkel; Eisse Mensink; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (ISSCC, 2007)

Cognitive radios for dynamic spectrum access - polyphase multipath radio circuits for dynamic spectrum access. - Eric A. M. Klumperink; Rameswor Shrestha; Eisse Mensink; Vincent J. Arkesteijn; Bram Nauta (IEEE Commun. Mag., 2007)

Message from the Incoming Editor-in-Chief. - Bram Nauta (IEEE J. Solid State Circuits, 2007)

Low-Frequency Noise Phenomena in Switched MOSFETs. - Arnoud P. van der Wel; Eric A. M. Klumperink; Jay S. Kolhatkar; Eric Hoekstra; Martijn F. Snoeij; Cora Salm; Hans Wallinga; Bram Nauta (IEEE J. Solid State Circuits, 2007)

Analytical Design Equations for Class-E Power Amplifiers. - Mustafa Acar; Anne-Johan Annema; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Optimal Positions of Twists in Global On-Chip Differential Interconnects. - Eisse Mensink; Daniël Schinkel; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A general weak nonlinearity model for LNAs. - Wei Cheng; Anne-Johan Annema; Jeroen A. Croon; Dirk B. M. Klaassen; Bram Nauta (CICC, 2008)

A multi-step P-cell for LNA design automation. - Wei Cheng; Anne-Johan Annema; Bram Nauta (ISCAS, 2008)

Digital Detection of Oxide Breakdown and Life-Time Extension in Submicron CMOS Technology. - Mustafa Acar; Anne-Johan Annema; Bram Nauta (ISSCC, 2008)

A Wideband Balun LNA I/Q-Mixer combination in 65nm CMOS. - Stephan C. Blaakmeer; Eric A. M. Klumperink; Domine Leenaerts; Bram Nauta (ISSCC, 2008)

A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC. - Michiel van Elzakker; Ed van Tuijl; Paul F. J. Geraedts; Daniël Schinkel; Eric A. M. Klumperink; Bram Nauta (ISSCC, 2008)

A 90μW 12MHz Relaxation Oscillator with a -162dB FOM. - Paul F. J. Geraedts; Ed van Tuijl; Eric A. M. Klumperink; Gerard Wienk; Bram Nauta (ISSCC, 2008)

A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection. - Zhiyu Ru; Eric A. M. Klumperink; Bram Nauta (ISSCC, 2008)

Wideband Balun-LNA With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling. - Stephan C. Blaakmeer; Eric A. M. Klumperink; Domine M. W. Leenaerts; Bram Nauta (IEEE J. Solid State Circuits, 2008)

The Blixer, a Wideband Balun-LNA-I/Q-Mixer Topology. - Stephan C. Blaakmeer; Eric A. M. Klumperink; Domine M. W. Leenaerts; Bram Nauta (IEEE J. Solid State Circuits, 2008)

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS. - Simon M. Louwsma; A. J. M. van Tuijl; Maarten Vertregt; Bram Nauta (IEEE J. Solid State Circuits, 2008)

Retraction of Papers With Falsified Information. - Bram Nauta; Willy Sansen (IEEE J. Solid State Circuits, 2008)

An Automatic Antenna Tuning System Using Only RF Signal Amplitudes. - Ettore Lorenzo Firrao; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation. - Xiang Gao 002; Bram Nauta; Eric A. M. Klumperink (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Theoretical Analysis of Highly Linear Tunable Filters Using Switched-Resistor Techniques. - Amorn Jiraseree-amornkun; Apisak Worapishet; Eric A. M. Klumperink; Bram Nauta; Wanlop Surakampontorn (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A Two-Stage Approach to Harmonic Rejection Mixing Using Blind Interference Cancellation. - Niels A. Moseley; Eric A. M. Klumperink; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A 200 µA duty-cycled PLL for wireless sensor nodes. - Salvatore Drago; Domine Leenaerts; Bram Nauta; Fabio Sebastiano; Kofi A. A. Makinwa; Lucien J. Breems (ESSCIRC, 2009)

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior. - Paul Veldhorst; George Goksun; Anne-Johan Annema; Bram Nauta; Berry A. J. Buter; Maarten Vertregt (ESSCIRC, 2009)

A sub-1V bandgap voltage reference in 32nm FinFET technology. - Anne-Johan Annema; Paul Veldhorst; Gerben Doornbos; Bram Nauta (ISSCC, 2009)

A 2.2GHz 7.6mW sub-sampling PLL with -126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS. - Xiang Gao 002; Eric A. M. Klumperink; Mounir Bohsali; Bram Nauta (ISSCC, 2009)

A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation. - Niels A. Moseley; Zhiyu Ru; Eric A. M. Klumperink; Bram Nauta (ISSCC, 2009)

A software-defined radio receiver architecture robust to out-of-band interference. - Zhiyu Ru; Eric A. M. Klumperink; Gerard Wienk; Bram Nauta (ISSCC, 2009)

A 0.2-to-2.0GHz 65nm CMOS receiver without LNA achieving ≫11dBm IIP3 and ≪6.5 dB NF. - Michiel C. M. Soer; Eric A. M. Klumperink; Zhiyu Ru; Frank E. van Vliet; Bram Nauta (ISSCC, 2009)

A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2. - Xiang Gao 002; Eric A. M. Klumperink; Mounir Bohsali; Bram Nauta (IEEE J. Solid State Circuits, 2009)

New Associate Editor. - Bram Nauta (IEEE J. Solid State Circuits, 2009)

New Associate Editors. - Bram Nauta (IEEE J. Solid State Circuits, 2009)

Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference. - Zhiyu Ru; Niels A. Moseley; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2009)

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios. - Fabio Sebastiano; Lucien J. Breems; Kofi A. A. Makinwa; Salvatore Drago; Domine M. W. Leenaerts; Bram Nauta (IEEE J. Solid State Circuits, 2009)

A Wideband Supply Modulator for 20 MHz RF Bandwidth Polar PAs in 65 nm CMOS. - Rameswor Shrestha; Ronan A. R. van der Zee; Anton de Graauw; Bram Nauta (IEEE J. Solid State Circuits, 2009)

Spurious-Free Dynamic Range of a Uniform Quantizer. - Mark S. Oude Alink; André B. J. Kokkeler; Eric A. M. Klumperink; Kenneth C. Rovers; Gerard J. M. Smit; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Impulse-Based Scheme for Crystal-Less ULP Radios. - Salvatore Drago; Fabio Sebastiano; Lucien J. Breems; Domine Leenaerts; Kofi A. A. Makinwa; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops. - Xiang Gao 002; Eric A. M. Klumperink; Paul F. J. Geraedts; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Low-Power, High-Speed Transceivers for Network-on-Chip Communication. - Daniël Schinkel; Eisse Mensink; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Time delay circuits: A quality criterion for delay variations versus frequency. - Seyed Kasra Garakoui; Eric A. M. Klumperink; Bram Nauta; Frank E. van Vliet (ISCAS, 2010)

A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with -82dBm sensitivity for crystal-less wireless sensor nodes. - Salvatore Drago; Domine M. W. Leenaerts; Fabio Sebastiano; Lucien J. Breems; Kofi A. A. Makinwa; Bram Nauta (ISSCC, 2010)

Spur-reduction techniques for PLLs using sub-sampling phase detection. - Xiang Gao 002; Eric A. M. Klumperink; Gerard Socci; Mounir Bohsali; Bram Nauta (ISSCC, 2010)

A 1.2V 10µW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from -70°C to 125°C. - Fabio Sebastiano; Lucien J. Breems; Kofi A. A. Makinwa; Salvatore Drago; Domine Leenaerts; Bram Nauta (ISSCC, 2010)

A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS. - Salvatore Drago; Domine Leenaerts; Bram Nauta; Fabio Sebastiano; Kofi A. A. Makinwa; Lucien J. Breems (IEEE J. Solid State Circuits, 2010)

A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s. - Michiel van Elzakker; Ed van Tuijl; Paul F. J. Geraedts; Daniël Schinkel; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2010)

Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector. - Xiang Gao 002; Eric A. M. Klumperink; Gerard Socci; Mounir Bohsali; Bram Nauta (IEEE J. Solid State Circuits, 2010)

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects. - Eisse Mensink; Daniël Schinkel; Eric A. M. Klumperink; Ed van Tuijl; Bram Nauta (IEEE J. Solid State Circuits, 2010)

Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio. - Zhiyu Ru; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2010)

A 300-800 MHz Tunable Filter and Linearized LNA Applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver. - Zhiyu Ru; Eric A. M. Klumperink; Carlos E. Saavedra; Bram Nauta (IEEE J. Solid State Circuits, 2010)

A 1.2-V 10-μ W NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2°C (3 Sigma ) From - 70°C to 125°C. - Fabio Sebastiano; Lucien J. Breems; Kofi A. A. Makinwa; Salvatore Drago; Domine Leenaerts; Bram Nauta (IEEE J. Solid State Circuits, 2010)

Unified Frequency-Domain Analysis of Switched-Series- RC Passive Mixers and Samplers. - Michiel C. M. Soer; Eric A. M. Klumperink; Pieter-Tjerk de Boer; Frank E. van Vliet; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A narrow-to-wideband scrambling technique increasing software radio receiver linearity. - Fabian van Houwelingen; Ed van Tuijl; Bram Nauta; Maarten Vertregt (ESSCIRC, 2011)

Effects of packaging and process spread on a mobility-based frequency reference in 0.16-μm CMOS. - Fabio Sebastiano; Lucien J. Breems; Kofi A. A. Makinwa; Salvatore Drago; Domine Leenaerts; Bram Nauta (ESSCIRC, 2011)

Jitter-Power minimization of digital frequency synthesis architectures. - Eric A. M. Klumperink; Ramen Dutta; Zhiyu Ru; Bram Nauta; Xiang Gao 002 (ISCAS, 2011)

Towards suppression of all harmonics in a polyphase multipath transmitter. - Saqib Subhan; Eric A. M. Klumperink; Bram Nauta (ISCAS, 2011)

A 1.0-to-4.0GHz 65nm CMOS four-element beamforming receiver using a switched-capacitor vector modulator with approximate sine weighting via charge redistribution. - Michiel C. M. Soer; Eric A. M. Klumperink; Bram Nauta; Frank E. van Vliet (ISSCC, 2011)

Exploring the Use of Two Antennas for Crosscorrelation Spectrum Sensing. - Mark S. Oude Alink; A. R. Smeenge; André B. J. Kokkeler; Eric A. M. Klumperink; Gerard J. M. Smit; Bram Nauta (VTC Fall, 2011)

Tunable High-Q N-Path Band-Pass Filters: Modeling and Verification. - Amir Ghaffari; Eric A. M. Klumperink; Michiel C. M. Soer; Bram Nauta (IEEE J. Solid State Circuits, 2011)

A 65-nm CMOS Temperature-Compensated Mobility-Based Frequency Reference for Wireless Sensor Networks. - Fabio Sebastiano; Lucien J. Breems; Kofi A. A. Makinwa; Salvatore Drago; Domine Leenaerts; Bram Nauta (IEEE J. Solid State Circuits, 2011)

Spatial Interferer Rejection in a Four-Element Beamforming Receiver Front-End With a Switched-Capacitor Vector Modulator. - Michiel C. M. Soer; Eric A. M. Klumperink; Bram Nauta; Frank E. van Vliet (IEEE J. Solid State Circuits, 2011)

Noise and Nonlinearity Modeling of Active Mixers for Fast and Accurate Estimation. - Wei Cheng; Anne-Johan Annema; Jeroen A. Croon; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Lowering the SNR Wall for Energy Detection Using Cross-Correlation. - Mark S. Oude Alink; André B. J. Kokkeler; Eric A. M. Klumperink; Gerard J. M. Smit; Bram Nauta (IEEE Trans. Veh. Technol., 2011)

Improving harmonic rejection for spectrum sensing using crosscorrelation. - Mark S. Oude Alink; André B. J. Kokkeler; Eric A. M. Klumperink; Zhiyu Ru; Wei Cheng; Bram Nauta (ESSCIRC, 2012)

Direct-digital modulation (DIDIMO) transmitter with -156dBc/Hz Rx-band noise using FIR structure. - Shuichi Fukuda; Shinji Miya; Miho Io; Koichi Hamashita; Bram Nauta (ESSCIRC, 2012)

A wideband IM3 cancellation technique for CMOS attenuators. - Wei Cheng; Mark S. Oude Alink; Anne-Johan Annema; Gerard Wienk; Bram Nauta (ISSCC, 2012)

A 0.3-to-1.2GHz tunable 4th-order switched gm-C bandpass filter with >55dB ultimate rejection and out-of-band IIP3 of +29dBm. - Milad Darvishi; Ronan A. R. van der Zee; Eric A. M. Klumperink; Bram Nauta (ISSCC, 2012)

A 1-to-2.5GHz phased-array IC based on gm-RC all-pass time-delay cells. - Seyed Kasra Garakoui; Eric A. M. Klumperink; Bram Nauta; Frank E. van Vliet (ISSCC, 2012)

8-Path tunable RF notch filters for blocker suppression. - Amir Ghaffari; Eric A. M. Klumperink; Bram Nauta (ISSCC, 2012)

A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communications. - Fawzi Houfaf; Mathieu Egot; Andreas Kaiser; Andreia Cathelin; Bram Nauta (ISSCC, 2012)

A 1.5-to-5.0GHz input-matched +2dBm P1dB all-passive switched-capacitor beamforming receiver front-end in 65nm CMOS. - Michiel C. M. Soer; Eric A. M. Klumperink; Bram Nauta; Frank E. van Vliet (ISSCC, 2012)

Active feedback receiver with integrated tunable RF channel selectivity, distortion cancelling, 48dB stopband rejection and >+12dBm wideband IIP3, occupying 2 in 65nm CMOS. - Shadi Youssef; Ronan A. R. van der Zee; Bram Nauta (ISSCC, 2012)

Widely Tunable 4th Order Switched Gm-C Band-Pass Filter Based on N-Path Filters. - Milad Darvishi; Ronan A. R. van der Zee; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2012)

Active Feedback Technique for RF Channel Selection in Front-End Receivers. - Shadi Youssef; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2012)

A CMOS-Compatible Spectrum Analyzer for Cognitive Radio Exploiting Crosscorrelation to Improve Linearity and Noise Performance. - Mark S. Oude Alink; Eric A. M. Klumperink; André B. J. Kokkeler; Michiel C. M. Soer; Gerard J. M. Smit; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model. - Wei Cheng; Mark S. Oude Alink; Anne-Johan Annema; Jeroen A. Croon; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

An integrated 80-V class-D power output stage with 94% efficiency in a 0.14µm SOI BCD process. - Haifeng Ma; Ronan A. R. van der Zee; Bram Nauta (ESSCIRC, 2013)

Session 1 overview: Plenary session. - Anantha P. Chandrakasan; Bram Nauta (ISSCC, 2013)

A 0.1-to-1.2GHz tunable 6th-order N-path channel-select filter with 0.6dB passband ripple and +7dBm blocker tolerance. - Milad Darvishi; Ronan A. R. van der Zee; Bram Nauta (ISSCC, 2013)

Simultaneous spatial and frequency-domain filtering at the antenna inputs achieving up to +10dBm out-of-band/beam P1dB. - Amir Ghaffari; Eric A. M. Klumperink; Frank E. van Vliet; Bram Nauta (ISSCC, 2013)

International technical program committee. - Bram Nauta; Trudy Stetzler (ISSCC, 2013)

EP1: Antiques from the innovations attic. - Trudy Stetzler; Anantha P. Chandrakasan; Bram Nauta (ISSCC, 2013)

Spectrum Sensing With High Sensitivity and Interferer Robustness Using Cross-Correlation Energy Detection. - Mark S. Oude Alink; André B. J. Kokkeler; Eric A. M. Klumperink; Gerard J. M. Smit; Bram Nauta (IEEE J. Emerg. Sel. Topics Circuits Syst., 2013)

A Wideband IM3 Cancellation Technique for CMOS Π- and T-Attenuators. - Wei Cheng; Mark S. Oude Alink; Anne-Johan Annema; Gerard Wienk; Bram Nauta (IEEE J. Solid State Circuits, 2013)

A Flicker Noise/IM3 Cancellation Technique for Active Mixer Using Negative Impedance. - Wei Cheng; Anne-Johan Annema; Gerard Wienk; Bram Nauta (IEEE J. Solid State Circuits, 2013)

Design of Active N-Path Filters. - Milad Darvishi; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2013)

Tunable N-Path Notch Filters for Blocker Suppression: Modeling and Verification. - Amir Ghaffari; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2013)

Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic. - Ramen Dutta; Eric A. M. Klumperink; Xiang Gao 002; Zhiyu Ru; Ronan A. R. van der Zee; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Frequency Limitations of First-Order gm - RC All-Pass Delay Circuits. - Seyed Kasra Garakoui; Eric A. M. Klumperink; Bram Nauta; Frank E. van Vliet (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

RF transconductor linearization technique robust to process, voltage and temperature variations. - Harish Kundur Subramaniyan; Eric A. M. Klumperink; Bram Nauta; Venkatesh Srinivasan; Ali Kiaei (A-SSCC, 2014)

Reconfigurable SDR front-end techniques. - Bram Nauta (CICC, 2014)

A 500MHz- 2.7 GHz 8-path weaver downconverter with harmonic rejection and embedded filtering. - Remko E. Struiksma; Eric A. M. Klumperink; Bram Nauta; Frank E. van Vliet (ESSCIRC, 2014)

17.1 An integrated 80V 45W class-D power amplifier with optimal-efficiency-tracking switching frequency regulation. - Haifeng Ma; Ronan A. R. van der Zee; Bram Nauta (ISSCC, 2014)

3.5 A 1.0-to-2.5GHz beamforming receiver with constant-Gm vector modulator consuming. - Michiel C. M. Soer; Eric A. M. Klumperink; Bram Nauta; Frank E. van Vliet (ISSCC, 2014)

A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. - Erik Olieman; Anne-Johan Annema; Bram Nauta (VLSIC, 2014)

Software defined radio receivers exploiting noise cancelling: A tutorial review. - Eric A. M. Klumperink; Bram Nauta (IEEE Commun. Mag., 2014)

An Ultra Low Energy FSK Receiver With In-Band Interference Robustness Exploiting a Three-Phase Chirped LO. - Ramen Dutta; Ronan A. R. van der Zee; André B. J. Kokkeler; Mark J. Bentum; Eric A. M. Klumperink; Bram Nauta (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Towards minimum achievable phase noise of relaxation oscillators. - Paul F. J. Geraedts; Ed J. M. van Tuijl; Eric A. M. Klumperink; Gerard J. M. Wienk; Bram Nauta (Int. J. Circuit Theory Appl., 2014)

Analog/RF Solutions Enabling Compact Full-Duplex Radios. - Björn Debaillie; Dirk-Jan van den Broek; Cristina Lavin; Barend van Liempd; Eric A. M. Klumperink; Carmen Palacios; Jan Craninckx; Bram Nauta; Aarno Pärssinen (IEEE J. Sel. Areas Commun., 2014)

A 4-Element Phased-Array System With Simultaneous Spatial- and Frequency-Domain Filtering at the Antenna Inputs. - Amir Ghaffari; Eric A. M. Klumperink; Frank E. van Vliet; Bram Nauta (IEEE J. Solid State Circuits, 2014)

Design and Analysis of a High-Efficiency High-Voltage Class-D Power Output Stage. - Haifeng Ma; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2014)

Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity. - Dlovan H. Mahrof; Eric A. M. Klumperink; Zhiyu Ru; Mark S. Oude Alink; Bram Nauta (IEEE J. Solid State Circuits, 2014)

Comments on "Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity". - P. V. Ananda Mohan; Eric A. M. Klumperink; Dlovan H. Mahrof; Bram Nauta (IEEE J. Solid State Circuits, 2014)

A 100-800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving <-40 dBc for ALL Harmonics. - Saqib Subhan; Eric A. M. Klumperink; Amir Ghaffari; Gerard J. M. Wienk; Bram Nauta (IEEE J. Solid State Circuits, 2014)

Sub-sampling PLL techniques. - Xiang Gao 002; Eric A. M. Klumperink; Bram Nauta (CICC, 2015)

Multiphase RF techniques in CMOS: Applied to beam-forming and full duplex receivers: CICC 2015 educational session. - Bram Nauta (CICC, 2015)

In-band full-duplex transceiver technology for 5G mobile networks. - Björn Debaillie; Barend van Liempd; Benjamin P. Hershberg; Jan Craninckx; Kari Rikkinen; D. J. van den Broek; Eric A. M. Klumperink; Bram Nauta (ESSCIRC, 2015)

19.2 A self-interference-cancelling receiver for in-band full-duplex wireless with low distortion under cancellation of strong TX leakage. - Dirk-Jan van den Broek; Eric A. M. Klumperink; Bram Nauta (ISSCC, 2015)

5.5 A forward-body-bias tuned 450MHz Gm-C 3rd-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply. - Joeri Lechevallier; Remko E. Struiksma; Hani Sherry; Andreia Cathelin; Eric A. M. Klumperink; Bram Nauta (ISSCC, 2015)

An In-Band Full-Duplex Radio Receiver With a Passive Vector Modulator Downmixer for Self-Interference Cancellation. - Dirk-Jan van den Broek; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2015)

Compact Cascadable g m -C All-Pass True Time Delay Cell With Reduced Delay Variation Over Frequency. - Seyed Kasra Garakoui; Eric A. M. Klumperink; Bram Nauta; Frank E. van Vliet (IEEE J. Solid State Circuits, 2015)

A High-Voltage Class-D Power Amplifier With Switching Frequency Regulation for Improved High-Efficiency Output Power Range. - Haifeng Ma; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2015)

An Interleaved Full Nyquist High-Speed DAC Technique. - Erik Olieman; Anne-Johan Annema; Bram Nauta (IEEE J. Solid State Circuits, 2015)

A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging. - Jiayoon Zhiyu Ru; Claudia Palattella; Paul F. J. Geraedts; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2015)

RF Transconductor Linearization Robust to Process, Voltage and Temperature Variations. - Harish Kundur Subramaniyan; Eric A. M. Klumperink; Venkatesh Srinivasan; Ali Kiaei; Bram Nauta (IEEE J. Solid State Circuits, 2015)

Analysis of the Signal Transfer and Folding in N-Path Filters With a Series Inductance. - Lammert Duipmans; Remko E. Struiksma; Eric A. M. Klumperink; Bram Nauta; Frank E. van Vliet (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

On the Minimum Number of States for Switchable Matching Networks. - Ettore Lorenzo Firrao; Anne-Johan Annema; Frank E. van Vliet; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Sensitive Method to Measure the Integral Nonlinearity of a Digital-to-Time Converter Based on Phase Modulation. - Claudia Palattella; Eric A. M. Klumperink; Jiayun Ru; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Random Telegraph Signal phenomena in avalanche mode diodes: Application to SPADs. - Vishal Agarwal; Anne-Johan Annema; Satadal Dutta; Raymond J. E. Hueting; Lis K. Nanver; Bram Nauta (ESSDERC, 2016)

26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilience. - Dawei Ye; Ronan A. R. van der Zee; Bram Nauta (ISSCC, 2016)

Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC). - Andrea Mazzanti; Bram Nauta; Stefan Rusu (IEEE J. Solid State Circuits, 2016)

A 915 MHz 175 µW Receiver Using Transmitted-Reference and Shifted Limiters for 50 dB In-Band Interference Tolerance. - Dawei Ye; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2016)

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. - Harijot Singh Bindra; Joeri Lechevallier; Anne-Johan Annema; Simon M. Louwsma; Ed van Tuijl; Bram Nauta (A-SSCC, 2017)

A digital sine-weighted switched-Gm mixer for single-clock power-scalable parallel receivers. - Reda Kasri; Eric A. M. Klumperink; Philippe Cathelin; Eric Toumier; Bram Nauta (CICC, 2017)

N-path filters and mixer-first receivers: A review. - Eric A. M. Klumperink; Hugo J. Westerveld; Bram Nauta (CICC, 2017)

Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking. - Dongyi Liao; Fa Foster Dai; Bram Nauta; Eric A. M. Klumperink (CICC, 2017)

An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. - Harijot Singh Bindra; Anne-Johan Annema; Simon M. Louwsma; Ed J. M. van Tuijl; Bram Nauta (ESSCIRC, 2017)

A 30fJ/comparison dynamic bias comparator. - Harijot Singh Bindra; Chris E. Lokin; Anne-Johan Annema; Bram Nauta (ESSCIRC, 2017)

24.3 A high-linearity CMOS receiver achieving +44dBm IIP3 and +13dBm B1dB for SAW-less LTE radio. - Yuanching Lien; Eric A. M. Klumperink; Bernard Tenbroek; Jon Strange; Bram Nauta (ISSCC, 2017)

Beamformer With Constant-Gm Vector Modulators and Its Spatial Intermodulation Distortion. - Michiel C. M. Soer; Eric A. M. Klumperink; Dirk-Jan van den Broek; Bram Nauta; Frank E. van Vliet (IEEE J. Solid State Circuits, 2017)

Hardware Implementation Overhead of Switchable Matching Networks. - Ettore Lorenzo Firrao; Anne-Johan Annema; Frank E. van Vliet; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Augmentation of Class-E PA Reliability under Load Mismatch Conditions. - Jeroen Ponte; Ali Ghahremani; Maikel Huiskamp; Anne-Johan Annema; Bram Nauta (ICECS, 2018)

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. - Harijot Singh Bindra; Chris E. Lokin; Daniël Schinkel; Anne-Johan Annema; Bram Nauta (IEEE J. Solid State Circuits, 2018)

Outphasing Class-E Power Amplifiers: From Theory to Back-Off Efficiency Improvement. - Ali Ghahremani; Anne-Johan Annema; Bram Nauta (IEEE J. Solid State Circuits, 2018)

A 2.4-GHz 16-Phase Sub-Sampling Fractional-N PLL With Robust Soft Loop Switching. - Dongyi Liao; Fa Foster Dai; Bram Nauta; Eric A. M. Klumperink (IEEE J. Solid State Circuits, 2018)

Enhanced-Selectivity High-Linearity Low-Noise Mixer-First Receiver With Complex Pole Pair Due to Capacitive Positive Feedback. - Yuanching Lien; Eric A. M. Klumperink; Bernard Tenbroek; Jon Strange; Bram Nauta (IEEE J. Solid State Circuits, 2018)

A Delay Spread Cancelling Waveform Characterizer for RF Power Amplifiers. - Maikel Huiskamp; Anne-Johan Annema; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Feedforward Phase Noise Cancellation Exploiting a Sub-Sampling Phase Detector. - Bart J. Thijssen; Eric A. M. Klumperink; Philip Quinlan; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. - Harijot Singh Bindra; Anne-Johan Annema; Gerard Wienk; Bram Nauta; Simon M. Louwsma (CICC, 2019)

A 0.06-3.4-MHz 92-μW Analog FIR Channel Selection Filter With Very Sharp Transition Band for IoT Receivers. - Bart J. Thijssen; Eric A. M. Klumperink; Philip Quinlan; Bram Nauta (ESSCIRC, 2019)

A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. - Harijot Singh Bindra; Anne-Johan Annema; Simon M. Louwsma; Bram Nauta (VLSI Circuits, 2019)

A Self-Oscillating Boosting Amplifier With Adaptive Soft Switching Control for Piezoelectric Transducers. - Saifullah Amir; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2019)

Fast & Energy Efficient Start-Up of Crystal Oscillators by Self-Timed Energy Injection. - Joeri Lechevallier; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2019)

High-Linearity Bottom-Plate Mixing Technique With Switch Sharing for N-path Filters/Mixers. - Yuanching Lien; Eric A. M. Klumperink; Bernard Tenbroek; Jon Strange; Bram Nauta (IEEE J. Solid State Circuits, 2019)

Improving Receiver Close-In Blocker Tolerance by Baseband Gm-C Notch Filtering. - Mohammed Abdulaziz; Eric A. M. Klumperink; Bram Nauta; Henrik Sjöland (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A +20 dBm Highly Efficient Linear Outphasing Class-E PA Without AM/AM and AM/PM Characterization Requirements. - Ali Ghahremani; Anne-Johan Annema; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Digital-to-Frequency Converters With a DTC: Theoretical Analysis of the Output SFDR. - Claudia Palattella; Eric A. M. Klumperink; Mark S. Oude Alink; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Colpitts-Based Frequency Reference Achieving a Single-Trim ± 120ppm Accuracy from -50 to 170°C. - Alexander S. Delke; Anne-Johan Annema; Mark S. Oude Alink; Yanyu Jin; Jos Verlinden; Bram Nauta (CICC, 2020)

30.4 A 370µW 5.5dB-NF BLE/BT5.0/IEEE 802.15.4-Compliant Receiver with >63dB Adjacent Channel Rejection at >2 Channels Offset in 22nm FDSOI. - Bart J. Thijssen; Eric A. M. Klumperink; Philip Quinlan; Bram Nauta (ISSCC, 2020)

EVM-based Performance Evaluation of Co-channel Interference Mitigation using Spatial Filtering for Digital MIMO Receivers. - Sajad Golabighezelahmad; Eric A. M. Klumperink; Bram Nauta (VTC Fall, 2020)

A Fully Passive RF Front End With 13-dB Gain Exploiting Implicit Capacitive Stacking in a Bottom-Plate N-Path Filter/Mixer. - Vijaya Kumar Purushothaman; Eric A. M. Klumperink; Berta Trullas Clavera; Bram Nauta (IEEE J. Solid State Circuits, 2020)

Low-Power Highly Selective Channel Filtering Using a Transconductor-Capacitor Analog FIR. - Bart J. Thijssen; Eric A. M. Klumperink; Philip Quinlan; Bram Nauta (IEEE J. Solid State Circuits, 2020)

EMI Reduction in Class-D Amplifiers by Actively Reducing PWM Ripple. - Christiaan E. Lokin; Ronan A. R. van der Zee; Daniël Schinkel; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Theory and Implementation of a Load-Mismatch Protective Class-E PA System. - Jeroen Ponte; Ali Ghahremani; Maikel Huiskamp; Anne-Johan Annema; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Analysis of Switched Capacitor Losses in Polar and Quadrature Switched Capacitor PAs. - Joep Zanen; Eric A. M. Klumperink; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Compensating Processing Delay in Excess of One Clock Cycle in Noise Shaping Loops Without Altering the Filter Topology. - Christiaan E. Lokin; Daniël Schinkel; Ronan A. R. van der Zee; Bram Nauta (IEEE Access, 2021)

Multi-Receiver Cross-Correlation Technique for (B)FSK Radios. - Vijaya Kumar Purushothaman; Mina R. M. Mikhael; Mark S. Oude Alink; Eric A. M. Klumperink; André B. J. Kokkeler; Bram Nauta (IEEE Access, 2021)

A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications. - Anoop Narayan Bhat; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2021)

A Single-Trim Frequency Reference Achieving ±120 ppm Accuracy From -50 °C to 170 °C. - Alexander S. Delke; Anne-Johan Annema; Mark S. Oude Alink; Yanyu Jin; Jos Verlinden; Bram Nauta (IEEE J. Solid State Circuits, 2021)

A 0.7-5.7 GHz Reconfigurable MIMO Receiver Architecture for Analog Spatial Notch Filtering Using Orthogonal Beamforming. - Sajad Golabighezelahmad; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2021)

Energy Efficient Startup of Crystal Oscillators Using Stepwise Charging. - Joeri Lechevallier; Harijot Singh Bindra; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2021)

2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter. - Bart J. Thijssen; Eric A. M. Klumperink; Philip Quinlan; Bram Nauta (IEEE J. Solid State Circuits, 2021)

Power Efficiency Model for MIMO Transmitters Including Memory Polynomial Digital Predistortion. - Joep Zanen; Eric A. M. Klumperink; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch. - Harijot Singh Bindra; Jeroen Ponte; Bram Nauta (ISSCC, 2022)

Quantifying the Trade-off Between Latency and Power Consumption in Bluetooth Low Energy and Its Mitigation by Using a Wake-Up Receiver. - Maryam Dodangeh; Mark S. Oude Alink; Bram Nauta (WF-IoT, 2022)

A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving p-p Output Swing Over 0.01-5.4-GHz for Direct RF Sampling Applications. - Anoop Narayan Bhat; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2022)

Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain. - Vijaya Kumar Purushothaman; Eric A. M. Klumperink; Roel Plompen; Bram Nauta (IEEE J. Solid State Circuits, 2022)

Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates. - Maikel Huiskamp; Mark S. Oude Alink; Bram Nauta; Anne-Johan Annema; Harijot Singh Bindra (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 50μW 2.45GHz Direct-Conversion RX with On-Chip LO with -84dBm Sensitivity for 1Mb/s GFSK. - Maryam Dodangeh; Mark S. Oude Alink; Jan Prummel; Bram Nauta (ESSCIRC, 2023)

Characterisation of Photodiodes in 22 nm FDSOI at 850 nm. - Jelle H. T. Bakker; Mark S. Oude Alink; Jurriaan Schmitz; Bram Nauta (ESSDERC, 2023)

Inverter Chain Buffer Optimization for N-path Filter Switch Drivers and Validation through Simulations in 22nm FD-SOI Technology. - Wouter T. Overeem; Mark S. Oude Alink; Bram Nauta (ISCAS, 2023)

A Predistortion-Less Digital MIMO Transmitter With DTC-Based Quadrature Imbalance Compensation. - Joep Zanen; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2023)

Hardware Implementations for Voice Activity Detection: Trends, Challenges and Outlook. - Shubham Yadav; Patrice Abbie D. Legaspi; Mark S. Oude Alink; André B. J. Kokkeler; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Single-Trim Frequency Reference System With 0.7 ppm/°C From -63 °C to 165 °C Consuming 210 μW at 70 MHz. - Alexander S. Delke; Thomas J. Hoen; Anne-Johan Annema; Yanyu Jin; Jos Verlinden; Bram Nauta (IEEE J. Solid State Circuits, 2023)

1.2 Racing Down the Slopes of Moore's Law. - Bram Nauta (ISSCC, 2024)

5.5 A Stacking Mixer-First Receiver Achieving >20dBm Adjacent-Channel IIP3 Consuming less than 25mW. - Stef van Zanten; Ronan A. R. van der Zee; Bram Nauta (ISSCC, 2024)

A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI. - Josef Heel; Harijot Singh Bindra; Simon M. Louwsma; Alessandro Dezzani; Bram Nauta (ISSCC, 2025)

Analysis and Design of a Low-Loss 1-10 GHz Capacitive Stacking N-Path Filter/Mixer. - Emiel Zijlma; Stef van Zanten; Roel Plompen; Eric A. M. Klumperink; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2025)

A Dual-Alternating-Slope Digital-to-Time Converter Leveraging Mismatch to Improve Delay Step Size. - Nimit Jain; Eric A. M. Klumperink; Harm van Rumpt; Bram Nauta (IEEE J. Solid State Circuits, 2025)

A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection. - Viswesh Kendae Ramkumar; Maikel Huiskamp; Harijot Singh Bindra; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2025)

Selectivity Versus Noise Trade-Offs in Resistively Driven Passive Switched-Capacitor Infinite Impulse Response Low-Pass Filters. - Roel Plompen; Jeroen Ponte; Stef van Zanten; Eric A. M. Klumperink; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Capacitive Stacking Mixer-First Receiver With Higher Order Capacitive Feedback. - Stef van Zanten; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2025)