Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM. - Pavel Poliakov; Ankur Anchlia; Marie Garcia Bardon; Bram Rooseleer; Bart De Wachter; Nadine Collaert; Koen van der Zanden; Wim Dehaene; Diederik Verkest; Miguel Corbalan Miranda (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link. - Bram Rooseleer; Stefan Cosemans; Wim Dehaene (IEEE J. Solid State Circuits, 2012)

A 40 nm, 454MHz 114 fJ/bit area-efficient SRAM memory with integrated charge pump. - Bram Rooseleer; Wim Dehaene (ESSCIRC, 2013)

A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration. - Ioannis A. Papistas; Stefan Cosemans; Bram Rooseleer; Jonas Doevenspeck; Myung Hee Na; Arindam Mallik; Peter Debacker; Diederik Verkest (CICC, 2021)

11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge. - Pascal Alexander Hager; Bert Moons; Stefan Cosemans; Ioannis A. Papistas; Bram Rooseleer; Jeroen Van Loon; Roel Uytterhoeven; Florian Zaruba; Spyridoula Koumousi; Milos Stanisavljevic; Stefan Mach; Sebastiaan Mutsaards; et al. (ISSCC, 2024)