Architecture of the Scalable Communications Core's Network on Chip. - David Arditti Ilitzky; Jeffrey D. Hoffman; Anthony Chun; Brando Perez Esparza (IEEE Micro, 2007)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)

19.1 A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers. - Bishnu Patra; Jeroen P. G. van Dijk; Sushil Subramanian; Andrea Corna; Xiao Xue 004; Charles Jeon; Farhana Sheikh; Esdras Juarez Hernandez; Brando Perez Esparza; Huzaifa Rampurawala; Brent R. Carlton; Nodar Samkharadze; et al. (ISSCC, 2020)

A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons. - Jeroen Petrus Gerardus van Dijk; Bishnu Patra; Sushil Subramanian; Xiao Xue 004; Nodar Samkharadze; Andrea Corna; Charles Jeon; Farhana Sheikh; Esdras Juarez Hernandez; Brando Perez Esparza; Huzaifa Rampurawala; Brent R. Carlton; et al. (IEEE J. Solid State Circuits, 2020)

A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology. - Jong Seok Park 001; Sushil Subramanian; Lester Lampert; Todor Mladenov; Ilya Klotchkov; Dileep Kurian; Esdras Juárez-Hernández; Brando Perez Esparza; Sirisha Rani Kale; K. T. Asma Beevi; Shavindra P. Premaratne; Thomas Watson 006; et al. (ISSCC, 2021)

A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits. - Jongseok Park 001; Sushil Subramanian; Lester Lampert; Todor Mladenov; Ilya Klotchkov; Dileep Kurian; Esdras Juarez Hernandez; Brando Perez Esparza; Sirisha Rani Kale; K. T. Asma Beevi; Shavindra P. Premaratne; Thomas Watson 006; et al. (IEEE J. Solid State Circuits, 2021)

A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Arun Radhakrishnan; Alejandro Cardenas Lopez; Jainaveen Sundaram; Vinayak Honkote; Leonid Azarenkov; Dan Lake; Jaykant Timbadiya; Mikhail J. Moiseev; et al. (ISSCC, 2025)