A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. - Ruggero Castagnetti; R. Venkatraman; Brandon Bartz; Carl Monzel; T. Briscoe; Andres Teene; S. Ramesh 004 (ISQED, 2005)

Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs. - Balaji Narasimham; Jung K. Wang; Narayana Vedula; Saket Gupta; Brandon Bartz; Carl Monzel; Indranil Chatterjee; Bharat L. Bhuva; Ronald D. Schrimpf; Robert A. Reed (IRPS, 2015)