FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template. - Niket Kumar Choudhary; Salil V. Wadhavkar; Tanmay A. Shah; Hiran Mayukh; Jayneel Gandhi; Brandon H. Dwiel; Sandeep Navada; Hashem Hashemi Najaf-abadi; Eric Rotenberg (ISCA, 2011)

FPGA modeling of diverse superscalar processors. - Brandon H. Dwiel; Niket Kumar Choudhary; Eric Rotenberg (ISPASS, 2012)

A physical design study of fabscalar-generated superscalar cores. - Niket K. Choudhary; Brandon H. Dwiel; Eric Rotenberg (VLSI-SoC, 2012)

FabScalar: Automating Superscalar Core Design. - Niket Kumar Choudhary; Salil V. Wadhavkar; Tanmay A. Shah; Hiran Mayukh; Jayneel Gandhi; Brandon H. Dwiel; Sandeep Navada; Hashem Hashemi Najaf-abadi; Eric Rotenberg (IEEE Micro, 2012)

Rationale for a 3D heterogeneous multi-core processor. - Eric Rotenberg; Brandon H. Dwiel; Elliott Forbes; Zhenqian Zhang; Randy Widialaksono; Rangeen Basu Roy Chowdhury; Nyunyi M. Tshibangu; Steve Lipa; W. Rhett Davis; Paul D. Franzon (ICCD, 2013)

Hetero2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors. - Shivam Priyadarshi; Niket K. Choudhary; Brandon H. Dwiel; Ankita Upreti; Eric Rotenberg; William Rhett Davis; Paul D. Franzon (ISQED, 2013)

Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores. - Elliott Forbes; Niket Kumar Choudhary; Brandon H. Dwiel; Eric Rotenberg (ICCD, 2014)

Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor. - Elliott Forbes; Zhenqian Zhang; Randy Widialaksono; Brandon H. Dwiel; Rangeen Basu Roy Chowdhury; Vinesh Srinivasan; Steve Lipa; Eric Rotenberg; W. Rhett Davis; Paul D. Franzon (Hot Chips Symposium, 2015)