Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs. - Brandon Noia; Krishnendu Chakrabarty; Yuan Xie 001 (ICCD, 2009)

Test-architecture optimization for TSV-based 3D stacked ICs. - Brandon Noia; Sandeep Kumar Goel; Krishnendu Chakrabarty; Erik Jan Marinissen; Jouke Verbree (ETS, 2010)

Optimization methods for post-bond die-internal/external testing in 3D stacked ICs. - Brandon Noia; Krishnendu Chakrabarty; Erik Jan Marinissen (ITC, 2010)

Pre-bond testing of die logic and TSVs in high performance 3D-SICs. - Brandon Noia; Krishnendu Chakrabarty (3DIC, 2011)

Identification of Defective TSVs in Pre-Bond Testing of 3D ICs. - Brandon Noia; Krishnendu Chakrabarty (Asian Test Symposium, 2011)

Testing and Design-for-Testability Techniques for 3D Integrated Circuits. - Brandon Noia; Krishnendu Chakrabarty (Asian Test Symposium, 2011)

Pre-bond probing of TSVs in 3D stacked ICs. - Brandon Noia; Krishnendu Chakrabarty (ITC, 2011)

Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips. - Brandon Noia; Krishnendu Chakrabarty (IET Comput. Digit. Tech., 2011)

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. - Brandon Noia; Krishnendu Chakrabarty; Sandeep Kumar Goel; Erik Jan Marinissen; Jouke Verbree (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Scan test of die logic in 3D ICs using TSV probing. - Brandon Noia; Shreepad Panth; Krishnendu Chakrabarty; Sung Kyu Lim (ITC, 2012)

Optimization Methods for Post-Bond Testing of 3D Stacked ICs. - Brandon Noia; Krishnendu Chakrabarty; Erik Jan Marinissen (J. Electron. Test., 2012)

Face-to-face bus design with built-in self-test in 3D ICs. - Zhenqian Zhang; Brandon Noia; Krishnendu Chakrabarty; Paul D. Franzon (3DIC, 2013)

Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs. - Brandon Noia; Krishnendu Chakrabarty (VTS, 2013)

Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs. - Brandon Noia; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs. - Brandon Noia; Krishnendu Chakrabarty (Springer, 2014)

Test and Design-for-Testability Solutions for 3D Integrated Circuits. - Krishnendu Chakrabarty; Mukesh Agrawal 001; Sergej Deutsch; Brandon Noia; Ran Wang 002; Fangming Ye (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

Retiming for Delay Recovery After DfT Insertion on Interdie Paths in 3-D ICs. - Brandon Noia; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs. - Brandon Noia (2014)

Scan Test of Die Logic in 3-D ICs Using TSV Probing. - Brandon Noia; Shreepad Panth; Krishnendu Chakrabarty; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2015)