Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias. - Breeta SenGupta; Urban Ingelsson; Erik Larsson (VLSI Design, 2012)

Scheduling Tests for 3D Stacked Chips under Power Constraints. - Breeta SenGupta; Urban Ingelsson; Erik Larsson (J. Electron. Test., 2012)

Test planning and test access mechanism design for stacked chips using ILP. - Breeta SenGupta; Erik Larsson (VTS, 2014)

Test Planning for Core-based Integrated Circuits under Power Constraints. - Breeta SenGupta; Dimitar Nikolov; Urban Ingelsson; Erik Larsson (J. Electron. Test., 2017)

Test Flow Selection for Stacked Integrated Circuits. - Breeta SenGupta; Dimitar Nikolov; Assmitra Dash; Erik Larsson (J. Electron. Test., 2019)

Test Cost Reduction of 3D Stacked ICs: Test Planning and Test Flow Selection. - Breeta SenGupta (2020)