A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter. - Brett Mathis; James E. Stine (ASAP, 2019)

A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter. - Brett Mathis; James E. Stine (ISVLSI, 2019)

Implementation of High Performance IEEE 754-Posit Conversion Hardware. - Brett Mathis; James E. Stine (ISCAS, 2022)