A parameterized VLSI video-rate histogram processor. - Brian C. Richards; Alex Sherstinsky; Robert W. Brodersen (ICASSP, 1987)

Hardware for Hidden Markov-Model-Based, Large-Vocabulary Real-Time Speech Recognition. - Mitch Weintraub; G. Chen; J. Mankoski; Hy Murveit; Anton Stölzle; Shankar Narayanaswamy; P. Schrupp; Brian C. Richards; Jan M. Rabaey; Robert W. Brodersen (HLT, 1990)

An integrated CAD system for algorithm-specific IC design. - C. Bernard Shung; Rajeev Jain; Ken Rimey; Edward Wang; Mani B. Srivastava; Brian C. Richards; Erik Lettang; Syed Khalid Azim; Lars E. Thon; Paul N. Hilfinger; Jan M. Rabaey; Robert W. Brodersen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Research challenges in wireless multimedia. - Robert W. Brodersen; Thomas D. Burd; Fred L. Burghardt; Andrew J. Burstein; Anantha P. Chandrakasan; Roger Doering; Shankar Narayanaswamy; Trevor Pering; Brian C. Richards; Thomas E. Truman; Jan M. Rabaey (PIMRC, 1994)

A prototype user interface for a mobile multimedia terminal. - Allan Christian Long Jr.; Shankar Narayanaswamy; Andrew J. Burstein; Richard Han 001; Ken Lutz; Brian C. Richards; Samuel Sheng; Robert W. Brodersen; Jan M. Rabaey (CHI 95 Conference Companion, 1995)

Design of Wireless Portable Systems. - Eric A. Brewer; Thomas D. Burd; Frederick L. Burghard; Andrew J. Burstein; Roger Doering; Ken Lutz; Shankar Narayanaswamy; Trevor Pering; Brian C. Richards; Thomas E. Truman; Randy H. Katz; Jan M. Rabaey; et al. (COMPCON, 1995)

Implementation of BEE: a real-time large-scale hardware emulation engine. - Chen Chang; Kimmo Kuusilinna; Brian C. Richards; Robert W. Brodersen (FPGA, 2003)

Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment. - Chen Chang; Kimmo Kuusilinna; Brian C. Richards; Allen Chen; Nathan Chan; Robert W. Brodersen; Borivoje Nikolic (IEEE International Workshop on Rapid System Prototyping, 2003)

Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications. - Kimmo Kuusilinna; Chen Chang; M. Josephine Ammer; Brian C. Richards; Robert W. Brodersen (EURASIP J. Adv. Signal Process., 2003)

Describing MIMO designs for rapid prototyping in the BEE environment. - Kimmo Kuusilinna; Chen Chang; Hans-Martin Blüthgen; Danijela Cabric; Brian C. Richards; Robert W. Brodersen (EUSIPCO, 2004)

ASIC Design and Verification in an FPGA Environment. - Dejan Markovic; Chen Chang; Brian C. Richards; Hayden Kwok-Hay So; Borivoje Nikolic; Robert W. Brodersen (CICC, 2007)

A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications. - Brian C. Richards; Nicola Nicolici; Henry Chen; Kevin Chao; Robert Abiad; Dan Werthimer; Borivoje Nikolic (CICC, 2009)

A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band. - Ji-Hoon Park; Brian C. Richards; Borivoje Nikolic (IEEE J. Solid State Circuits, 2011)

Chisel: constructing hardware in a Scala embedded language. - Jonathan Bachrach; Huy Vo; Brian C. Richards; Yunsup Lee; Andrew Waterman; Rimas Avizienis; John Wawrzynek; Krste Asanovic (DAC, 2012)

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. - Yunsup Lee; Brian Zimmer; Andrew Waterman; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Henry Cook; Rimas Avizienis; et al. (Hot Chips Symposium, 2015)

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (VLSIC, 2015)

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Steven Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (IEEE J. Solid State Circuits, 2016)

An Agile Approach to Building RISC-V Microprocessors. - Yunsup Lee; Andrew Waterman; Henry Cook; Brian Zimmer; Ben Keller; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Rimas Avizienis; et al. (IEEE Micro, 2016)

A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET. - Angie Wang; Brian C. Richards; Daniel Palmer Dabbelt; Howard Mao; Stevo Bailey; Jaeduk Han; Eric Chang; James Dunn 003; Elad Alon; Borivoje Nikolic (A-SSCC, 2017)

A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. - Stevo Bailey; Jaeduk Han; Paul Rigge; Richard Lin; Eric Chang; Howard Mao; Zhongkai Wang; Chick Markley; Adam M. Izraelevitz; Angie Wang; Nathan Narevsky; Woo-Rham Bae; et al. (A-SSCC, 2018)

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. - Steven Bailey; Paul Rigge; Jaeduk Han; Richard Lin; Eric Chang; Howard Mao; Zhongkai Wang; Chick Markley; Adam M. Izraelevitz; Angie Wang; Nathan Narevsky; Woo-Rham Bae; et al. (IEEE J. Solid State Circuits, 2019)

4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET. - Colin Schmidt 001; John Charles Wright; Zhongkai Wang; Eric Chang; Albert J. Ou; Woo-Rham Bae; Sean Huang; Anita Flynn; Brian C. Richards; Krste Asanovic; Elad Alon; Borivoje Nikolic (ISSCC, 2021)

An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET. - Colin Schmidt 001; John Charles Wright; Zhongkai Wang; Eric Chang; Albert J. Ou; Woorham Bae; Sean Huang; Vladimir M. Milovanovic; Anita Flynn; Brian C. Richards; Krste Asanovic; Elad Alon; et al. (IEEE J. Solid State Circuits, 2022)

HDBinaryCore: A 28nm 2048-bit Hyper-Dimensional biosignal classifier achieving 25 nJ/prediction for EMG hand-gesture recognition. - Sohum Datta; Brian C. Richards; Harrison Liew; Youbin Kim; Daniel Sun 005; Jan M. Rabaey (ESSCIRC, 2023)