Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology. - Brian Campbell 004; James Burnette; Naveen Javarappa; Vincent von Kaenel (CICC, 2007)

A 2GHz, 7W (max) 64b PowerTM Microprocessor Core. - Daniel Murray; James Burnette; Brian Campbell 004; Mark Chung; Bruce Fernandes; Subhendra Ghosh; Rajat Goel; Greg Hess; Hang Huang; Zhibin Huang; Naveen Javarappa; Pradeep Kanapathipillai; et al. (CICC, 2007)

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems. - Zongjian Chen; Priya Ananthanarayanan; Sukalp Biswas; Brian Campbell 004; Hao Chen; Shaishav Desai; Dominic Go; Rajat Goel; Vincent von Kaenel; Jason Kassoff; Fabian Klass; Weichun Ku; et al. (ISSCC, 2007)