Analysis and modeling of CD variation for statistical static timing. - Brian Cline; Kaviraj Chopra; David T. Blaauw; Yu Cao (ICCAD, 2006)

Leakage power reduction using stress-enhanced layouts. - Vivek Joshi; Brian Cline; Dennis Sylvester; David T. Blaauw; Kanak Agarwal 001 (DAC, 2008)

Transistor-Specific Delay Modeling for SSTA. - Brian Cline; Kaviraj Chopra; David T. Blaauw; Andres Torres; Savithri Sundareswaran (DATE, 2008)

STEEL: a technique for stress-enhanced standard cell library design. - Brian Cline; Vivek Joshi; Dennis Sylvester; David T. Blaauw (ICCAD, 2008)

Stress aware layout optimization. - Vivek Joshi; Brian Cline; Dennis Sylvester; David T. Blaauw; Kanak Agarwal 001 (ISPD, 2008)

Exploring Variability and Performance in a Sub-200-mV Processor. - Scott Hanson; Bo Zhai; Mingoo Seok; Brian Cline; Kevin Zhou; Meghna Singhal; Michael Minuth; Javin Olson; Leyla Nazhandali; Todd M. Austin; Dennis Sylvester; David T. Blaauw (IEEE J. Solid State Circuits, 2008)

Mechanical Stress Aware Optimization for Leakage Power Reduction. - Vivek Joshi; Brian Cline; Dennis Sylvester; David T. Blaauw; Kanak Agarwal 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Exploring sub-20nm FinFET design with predictive technology models. - Saurabh Sinha; Greg Yeric; Vikas Chandra; Brian Cline; Yu Cao 001 (DAC, 2012)

Design benchmarking to 7nm with FinFET predictive technology models. - Saurabh Sinha; Brian Cline; Greg Yeric; Vikas Chandra; Yu Cao 001 (ISLPED, 2012)

The past present and future of design-technology co-optimization. - Greg Yeric; Brian Cline; Saurabh Sinha; David Pietromonaco; Vikas Chandra; Rob Aitken (CICC, 2013)

DFM is dead - Long live DFM. - Robert C. Aitken; David Pietromonaco; Brian Cline (ICCD, 2014)

Physical design and FinFETs. - Robert C. Aitken; Greg Yeric; Brian Cline; Saurabh Sinha; Lucian Shifren; Imran Iqbal; Vikas Chandra (ISPD, 2014)

Power benefit study of monolithic 3D IC at the 7nm technology node. - Kyungwook Chang; Kartik Acharya; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (ISLPED, 2015)

Circuit design perspectives for Ge FinFET at 10nm and beyond. - Saurabh Sinha; Lucian Shifren; Vikas Chandra; Brian Cline; Greg Yeric; Robert C. Aitken; Bingjie Cheng; Andrew R. Brown; Craig Riddet; C. Alexandar; Campbell Millar; Asen Asenov (ISQED, 2015)

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization. - Xiaoqing Xu; Brian Cline; Greg Yeric; Bei Yu 001; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Match-making for monolithic 3D IC: finding the right technology node. - Kyungwook Chang; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (DAC, 2016)

Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability. - Nathaniel Ross Pinckney; Lucian Shifren; Brian Cline; Saurabh Sinha; Supreet Jeloka; Ronald G. Dreslinski; Trevor N. Mudge; Dennis Sylvester; David T. Blaauw (DAC, 2016)

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools. - Kyungwook Chang; Saurabh Sinha; Brian Cline; Raney Southerland; Michael Doherty; Greg Yeric; Sung Kyu Lim (ICCAD, 2016)

Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study. - Kwang Min Kim; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (ISLPED, 2016)

Monolithic 3D IC design: Power, performance, and area impact at 7nm. - Kartik Acharya; Kyungwook Chang; Bon Woong Ku; Shreepad Panth; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (ISQED, 2016)

Welcome. - Brian Cline; Saibal Mukhopadhyay; Peter J. Wright; Hai Li; Vinod Viswanath; Paul Wesling; Gang Qu 001; Ali Iranmanesh (ISQED, 2016)

Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. - Robert C. Aitken; Vikas Chandra; Brian Cline; Shidhartha Das; David Pietromonaco; Lucian Shifren; Saurabh Sinha; Greg Yeric (IET Comput. Digit. Tech., 2016)

ASAP7: A 7-nm finFET predictive process design kit. - Lawrence T. Clark; Vinay Vashishtha; Lucian Shifren; Aditya Gujja; Saurabh Sinha; Brian Cline; Chandarasekaran Ramamurthy; Greg Yeric (Microelectron. J., 2016)

Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper). - Xiaoqing Xu; Nishi Shah; Andrew Evans; Saurabh Sinha; Brian Cline; Greg Yeric (ICCAD, 2017)

DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node. - Jiaojiao Ou; Xiaoqing Xu; Brian Cline; Greg Yeric; David Z. Pan (ICCD, 2017)

Frequency and time domain analysis of power delivery network for monolithic 3D ICs. - Kyungwook Chang; Shidhartha Das; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (ISLPED, 2017)

Impact of FinFET on Near-Threshold Voltage Scalability. - Nathaniel Ross Pinckney; Supreet Jeloka; Ronald G. Dreslinski; Trevor N. Mudge; Dennis Sylvester; David T. Blaauw; Lucian Shifren; Brian Cline; Saurabh Sinha (IEEE Des. Test, 2017)

Redundant Local-Loop Insertion for Unidirectional Routing. - Xiaoqing Xu; Yibo Lin; Meng Li 004; Jiaojiao Ou; Brian Cline; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node. - Kyungwook Chang; Kartik Acharya; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. - Divya Prasad; Saurabh Sinha; Brian Cline; Steve Moore; Azad Naeemi (DAC, 2018)

Standard Cell Library Design and Optimization Methodology for ASAP7 PDK. - Xiaoqing Xu; Nishi Shah; Andrew Evans; Saurabh Sinha; Brian Cline; Greg Yeric (CoRR, 2018)

Enhanced 3D Implementation of an Arm® Cortex®-A Microprocessor. - Xiaoqing Xu; Mudit Bhargava; Steve Moore; Saurabh Sinha; Brian Cline (ISLPED, 2019)

System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. - Kyungwook Chang; Shidhartha Das; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. - Saurabh Sinha; Xiaoqing Xu; Mudit Bhargava; Shidhartha Das; Brian Cline; Greg Yeric (CoRR, 2020)

3D-Split SRAM: Enabling Generational Gains in Advanced CMOS. - Rahul Mathur; Mudit Bhargava; Heath Perry; Alberto Cestero; Frank Frederick; Shawn Hung; Chien-Ju Chao; Daniel Smith; Daniel Fisher; Norman Robson; Xiaoqing Xu; Pranavi Chandupatla; et al. (CICC, 2021)

A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance. - Rakshith Saligram; Divya Prasad; David Pietromonaco; Arijit Raychowdhury; Brian Cline (CICC, 2021)

Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture. - Lingjun Zhu; Tuan Ta; Rossana Liu; Rahul Mathur; Xiaoqing Xu; Shidhartha Das; Ankit Kaul; Alejandro Rico; Doug Joseph; Brian Cline; Sung Kyu Lim (ISLPED, 2021)

Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor. - Chi-Shuen Lee; Brian Cline; Saurabh Sinha; Greg Yeric; H.-S. Philip Wong (CoRR, 2021)

High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors. - Lingjun Zhu; Lennart Bamberg; Sai Surya Kiran Pentapati; Kyungwook Chang; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Brian Cline; Saurabh Sinha; Xiaoqing Xu; Alberto García-Ortiz; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

System technology co-optimization and design challenges for 3D IC. - Supreet Jeloka; Brian Cline; Shidhartha Das; Benoit Labbe; Alejandro Rico; Rainer Herberholz; Javier A. DeLaCruz; Rahul Mathur; Shawn Hung (CICC, 2022)

Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools. - Kyungwook Chang; Saurabh Sinha; Brian Cline; Greg Yeric; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)