Local Learning in RRAM Neural Networks with Sparse Direct Feedback Alignment. - Brian Crafton; Matt West 002; Padip Basnet; Eric Vogel; Arijit Raychowdhury (ISLPED, 2019)

Direct Feedback Alignment with Sparse Connections for Local Learning. - Brian Crafton; Abhinav Parihar; Evan Gebhardt; Arijit Raychowdhury (CoRR, 2019)

Hardware-Aware Pruning of DNNs using LFSR-Generated Pseudo-Random Indices. - Foroozan Karimzadeh; Ningyuan Cao; Brian Crafton; Justin Romberg; Arijit Raychowdhury (ISCAS, 2020)

Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics. - Brian Crafton; Samuel Spetalnick; Gauthaman Murali; Tushar Krishna; Sung Kyu Lim; Arijit Raychowdhury (VLSI-SOC, 2020)

Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics. - Brian Crafton; Samuel Spetalnick; Gauthaman Murali; Tushar Krishna; Sung Kyu Lim; Arijit Raychowdhury (VLSI-SoC (Selected Papers), 2020)

Counting Cards: Exploiting Weight and Variance Distributions for Robust Compute In-Memory. - Brian Crafton; Samuel Spetalnick; Arijit Raychowdhury (CoRR, 2020)

Hardware-Algorithm Co-Design Enabling Efficient Event-based Object Detection. - Brian Crafton; Andrew Paredes; Evan Gebhardt; Arijit Raychowdhury (AICAS, 2021)

Merged Logic and Memory Fabrics for AI Workloads. - Brian Crafton; Samuel Spetalnick; Arijit Raychowdhury (ASP-DAC, 2021)

CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation. - Brian Crafton; Samuel Spetalnick; Jong-Hyeok Yoon; Wei Wu; Carlos Tokunaga; Vivek De; Arijit Raychowdhury (A-SSCC, 2021)

Statistical Optimization of Compute In-Memory Performance Under Device Variation. - Brian Crafton; Samuel Spetalnick; Jong-Hyeok Yoon; Arijit Raychowdhury (ISLPED, 2021)

Automatic Generation of Translators for Packet-Based and Emerging Protocols. - Brian Crafton; Arijit Raychowdhury; Sung Kyu Lim (ISQED, 2021)

Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads. - Brian Crafton; Samuel Spetalnick; Yan Fang; Arijit Raychowdhury (IEEE Des. Test, 2021)

A Hardware-Friendly Approach Towards Sparse Neural Networks Based on LFSR-Generated Pseudo-Random Sequences. - Foroozan Karimzadeh; Ningyuan Cao; Brian Crafton; Justin Romberg; Arijit Raychowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Improving compute in-memory ECC reliability with successive correction. - Brian Crafton; Zishen Wan; Samuel Spetalnick; Jong-Hyeok Yoon; Wei Wu; Carlos Tokunaga; Vivek De; Arijit Raychowdhury (DAC, 2022)

Characterization and Mitigation of IR-Drop in RRAM-based Compute In-Memory. - Brian Crafton; Connor Talley; Samuel Spetalnick; Jong-Hyeok Yoon; Arijit Raychowdhury (ISCAS, 2022)

A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. - Muya Chang; Samuel D. Spetalnick; Brian Crafton; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2022)

A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range. - Samuel D. Spetalnick; Muya Chang; Brian Crafton; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2022)

Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem. - Ashwin Sanjay Lele; Muya Chang; Samuel D. Spetalnick; Brian Crafton; Arijit Raychowdhury; Yan Fang (DAC, 2023)

Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking. - Ashwin Sanjay Lele; Muya Chang; Samuel Spetalnick; Yan Fang; Brian Crafton; Shota Konno; Arijit Raychowdhury (ISCAS, 2023)

A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. - Muya Chang; Ashwin Sanjay Lele; Samuel D. Spetalnick; Brian Crafton; Shota Konno; Zishen Wan; Ashwin Bhat; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2023)

A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation. - Samuel D. Spetalnick; Muya Chang; Shota Konno; Brian Crafton; Ashwin Sanjay Lele; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (VLSI Technology and Circuits, 2023)

Overcoming Device Level Challenges to Enable Compute In-Memory with Emerging Non-Volatile Memory. - Brian Crafton (2023)

30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. - Samuel D. Spetalnick; Ashwin Sanjay Lele; Brian Crafton; Muya Chang; Sigang Ryu; Jong-Hyeok Yoon; Zhijian Hao; Azadeh Ansari; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2024)

A 28nm Approximate / Binary 6T CAM for Sequence Alignment. - Brian Crafton; Samuel D. Spetalnick; Muya Chang; Arijit Raychowdhury (VLSI Technology and Circuits, 2024)

A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. - Ashwin Sanjay Lele; Muya Chang; Samuel D. Spetalnick; Brian Crafton; Shota Konno; Zishen Wan; Ashwin Bhat; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2024)

Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. - Xiaoyu Sun 001; Weidong Cao 001; Brian Crafton; Kerem Akarvardar; Haruki Mori; Hidehiro Fujiwara; Hiroki Noguchi; Yu-Der Chih; Meng-Fan Chang; Yih Wang; Tsung-Yung Jonathan Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory. - Ying-Hao Wei; Zishen Wan; Brian Crafton; Samuel Spetalnick; Arijit Raychowdhury (ISCAS, 2025)

An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance. - Samuel D. Spetalnick; Ashwin Sanjay Lele; Brian Crafton; Muya Chang; Sigang Ryu; Jong-Hyeok Yoon; Zhijian Hao; Azadeh Ansari; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2025)