A Probabilistic Power Prediction Tool for the Xilinx 4000-Series FPGA. - Timothy Osmulski; Jeffrey T. Muehring; Brian F. Veale; Jack M. West; Hongping Li; Sirirut Vanichayobon; Seok-Hyun Ko; John K. Antonio; Sudarshan K. Dhall (IPDPS Workshops, 2000)

Code Re-ordering for a Class of Reconfigurable Microprocessors. - Brian F. Veale; John K. Antonio; Monte P. Tull (FPL, 2004)

Configuration Steering for a Reconfigurable Superscalar Processor. - Brian F. Veale; John K. Antonio; Monte P. Tull (IPDPS, 2005)

Dynamic configuration steering for a reconfigurable superscalar processor. - Nick A. Mould; Brian F. Veale; Monte P. Tull; John K. Antonio (IPDPS, 2006)

Selection of instruction set extensions for an FPGA embedded processor core. - Brian F. Veale; John K. Antonio; Monte P. Tull; Sean A. Jones (IPDPS, 2006)

Design of steering vectors for dynamically reconfigurable architectures. - Nick A. Mould; Brian F. Veale; John K. Antonio; Monte P. Tull; John R. Junger (IPDPS, 2008)

Characterization of System Services and Their Performance Impact in Multi-core Nodes. - Seetharami Seelam; Liana Fong; John Lewars; John Divirgilio; Brian F. Veale; Kevin J. Gildea (IPDPS, 2011)

IBM POWER9 system software. - Joefon Jann; Paul Mackerras; John M. Ludden; Michael Gschwind; Wade Ouren; Stuart Jacobs; Brian F. Veale; David Edelsohn (IBM J. Res. Dev., 2018)