Programmable floating-gate techniques for CMOS inverters. - Brian P. Degnan; Richard B. Wunderlich; Paul E. Hasler (ISCAS (3), 2005)

Capacitively-Biased Floating-Gate CMOS: a New Logic Family. - Richard B. Wunderlich; Brian P. Degnan; Paul E. Hasler (ISCAS, 2007)

Indirect Programming of Floating-Gate Transistors. - David W. Graham; Ethan Farquhar; Brian P. Degnan; Christal Gordon; Paul E. Hasler (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Passgate Resistance Estimation based on the Compact EKV Model and Effective Mobility. - Brian P. Degnan; Richard B. Wunderlich; Paul E. Hasler (ISCAS, 2009)

An Asynchronously Embedded Datapath for Performance Acceleration and Energy Efficiency. - Bo Marr; Brian P. Degnan; Paul E. Hasler; David V. Anderson (ISCAS, 2009)

Crossbar switch matrix for floating-gate programming over large current ranges. - Brian P. Degnan; Brian J. Duffy; Paul E. Hasler (ISCAS, 2010)

Live demonstration: Hardware and software infrastructure for a family of floating-gate based FPAAs. - Scott Koziol; Craig Schlottmann; Arindam Basu; Stephen Brink; Csaba Petre; Brian P. Degnan; Shubha Ramakrishnan; Paul E. Hasler; Aurele Balavoine (ISCAS, 2010)

Hardware and software infrastructure for a family of floating-gate based FPAAs. - Scott Koziol; Craig Schlottmann; Arindam Basu; Stephen Brink; Csaba Petre; Brian P. Degnan; Shubha Ramakrishnan; Paul E. Hasler; Aurele Balavoine (ISCAS, 2010)

Reducing offset errors in MITE systems by precise floating gate programming. - Craig Schlottmann; Brian P. Degnan; David Abramson 002; Paul E. Hasler (ISCAS, 2010)

Error Immune Logic for Low-Power Probabilistic Computing. - Bo Marr; Jason George; Brian P. Degnan; David V. Anderson; Paul E. Hasler (VLSI Design, 2010)

A Learning-Enabled Neuron Array IC Based Upon Transistor Channel Models of Biological Phenomena. - Stephen Brink; Stephen Nease; Paul E. Hasler; Shubha Ramakrishnan; Richard B. Wunderlich; Arindam Basu; Brian P. Degnan (IEEE Trans. Biomed. Circuits Syst., 2013)

Scaling Energy Per Operation via an Asynchronous Pipeline. - Bo Marr; Brian P. Degnan; Paul E. Hasler; David V. Anderson (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Temperature robust programmable subthreshold circuits through a balanced force approach. - Brian P. Degnan (2013)

Low-power, serial interface for power-constrained devices. - Brian P. Degnan; Jennifer Hasler (MWSCAS, 2015)

A 45 μW bias power, 34 dB gain reflection amplifier exploiting the tunneling effect for RFID applications. - Francesco Amato 002; Christopher W. Peterson; Brian P. Degnan; Gregory D. Durgin (IEEE RFID, 2015)

Asynchronous trigger modulation for RFID systems. - Brian P. Degnan; Gregory D. Durgin (RFID-TA, 2015)

On the temperature dependence of subthreshold currents in MOS electron inversion layers, revisited. - Brian P. Degnan; Jennifer Hasler (ISCAS, 2016)

Assessing Trends in Performance per Watt for Signal Processing Applications. - Brian P. Degnan; Bo Marr; Jennifer Hasler (IEEE Trans. Very Large Scale Integr. Syst., 2016)

On the Simon Cipher 4-block key schedule as a hash. - Brian P. Degnan; Gregory D. Durgin; Suigin Maeda (RFID, 2017)

A better channel code than FM0 for next-generation RFID. - Gregory D. Durgin; Brian P. Degnan (RFID, 2017)

Backscatter Ex-Nihilo: Single-component, Fully-passive Backscattering for Microcontrollers. - Stewart J. Thomas; Brian P. Degnan; Cristel Callupe Chavez; Billy Culver (RFID, 2020)